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    參數(shù)資料
    型號(hào): LTC2266CUJ-14#TRPBF
    廠商: Linear Technology
    文件頁數(shù): 8/32頁
    文件大?。?/td> 0K
    描述: IC ADC 14BIT 80MSPS DUAL 40QFN
    標(biāo)準(zhǔn)包裝: 2,000
    位數(shù): 14
    采樣率(每秒): 80M
    數(shù)據(jù)接口: Serial LVDS
    轉(zhuǎn)換器數(shù)目: 2
    功率耗散(最大): 257mW
    電壓電源: 單電源
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 40-WFQFN 裸露焊盤
    供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
    包裝: 帶卷 (TR)
    輸入數(shù)目和類型: 2 Differential; 2 Single-Ended
    配用: DC1371A-ND - BOARD USB DATA ACQUISITION HS
    LTC2268-14/
    LTC2267-14/LTC2266-14
    16
    22687614fa
    pin FuncTions
    AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input.
    AIN1–(Pin2):Channel1NegativeDifferentialAnalogInput.
    VCM1(Pin3):CommonModeBiasOutput,NominallyEqual
    to VDD/2. VCM should be used to bias the common mode
    of the analog inputs of channel 1. Bypass to ground with
    a 0.1F ceramic capacitor.
    REFH (Pins 4,5): ADC High Reference. Bypass to pins 6, 7
    with a 2.2F ceramic capacitor and to ground with a 0.1F
    ceramic capacitor.
    REFL (Pins 6,7): ADC Low Reference. Bypass to pins 4, 5
    with a 2.2F ceramic capacitor and to ground with a 0.1F
    ceramic capacitor.
    VCM2(Pin8):CommonModeBiasOutput,NominallyEqual
    to VDD/2. VCM should be used to bias the common mode
    of the analog inputs of channel 2. Bypass to ground with
    a 0.1F ceramic capacitor.
    AIN2+ (Pin 9): Channel 2 Positive Differential Analog
    Input.
    AIN2– (Pin 10): Channel 2 Negative Differential Analog
    Input.
    VDD (Pins 11, 12, 39, 40): 1.8V Analog Power Supply.
    Bypass to ground with 0.1F ceramic capacitors. Adjacent
    pins can share a bypass capacitor.
    ENC+ (Pin 13): Encode Input. Conversion starts on the
    rising edge.
    ENC(Pin 14): Encode Complement Input. Conversion
    starts on the falling edge.
    CS(Pin15):Inserialprogrammingmode,(PAR/SER=0V),
    CS is the serial interface chip select input. When CS is low,
    SCKisenabledforshiftingdataonSDIintothemodecontrol
    registers. In the parallel programming mode (PAR/SER =
    VDD), CS selects 2-lane or 1-lane output mode. CS can
    be driven with 1.8V to 3.3V logic.
    SCK (Pin 16): In serial programming mode, (PAR/SER =
    0V), SCK is the serial interface clock input. In the parallel
    programming mode (PAR/SER= VDD), SCK selects 3.5mA
    or 1.75mA LVDS output currents. SCK can be driven with
    1.8V to 3.3V logic.
    SDI (Pin 17): In serial programming mode, (PAR/SER =
    0V), SDI is the serial interface data input. Data on SDI is
    clocked into the mode control registers on the rising edge
    of SCK. In the parallel programming mode (PAR/SER =
    VDD), SDI can be used to power down the part. SDI can
    be driven with 1.8V to 3.3V logic.
    GND (Pins 18, 33, 37, Exposed Pad Pin 41): ADC Power
    Ground. The exposed pad must be soldered to the PCB
    ground.
    OGND (Pin 25): Output Driver Ground. Must be shorted
    to the ground plane by a very low inductance path. Use
    multiple vias close to the pin.
    OVDD (Pin 26): Output Driver Supply. Bypass to ground
    with a 0.1F ceramic capacitor.
    SDO (Pin 34): In serial programming mode, (PAR/SER
    = 0V), SDO is the optional serial interface data output.
    Data on SDO is read back from the mode control registers
    and can be latched on the falling edge of SCK. SDO is an
    open-drain NMOS output that requires an external 2k
    pull-up resistor to 1.8V – 3.3V. If read back from the mode
    control registers is not needed, the pull-up resistor is not
    necessary and SDO can be left unconnected. In the parallel
    programmingmode(PAR/SER=VDD),SDOisaninputthat
    enables internal 100Ω termination resistors on the digital
    outputs. When used as an input, SDO can be driven with
    1.8V to 3.3V logic through a 1k series resistor.
    PAR/SER (Pin 35): Programming Mode Selection Pin.
    Connecttogroundtoenabletheserialprogrammingmode.
    CS, SCK, SDI, SDO become a serial interface that control
    the A/D operating modes. Connect to VDD to enable the
    parallel programming mode where CS, SCK, SDI, SDO
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