For more information www.linear.com/LTC2262-12 FUNCTIONAL BLOCK DIAGRAM Figure 1" />
參數(shù)資料
型號(hào)： LTC2262IUJ-12#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 150MSPS 40-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 150M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 146mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分
配用： DC890B-ND - BOARD USB DATA COLLECTION
LTC2262-12
13
226212fc
For more information www.linear.com/LTC2262-12
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
DIFF
REF
AMP
REF
BUF
2.2F
0.1F
INTERNAL CLOCK SIGNALS
REFH
REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
ENC–
SHIFT REGISTER
AND CORRECTION
SDO
CS
OGND
OF
OVDD
D11
CLKOUT–
CLKOUT+
D0
226212 F01
INPUT
S/H
SENSE
VREF
AIN–
AIN+
1F
VCM
0.1F
VDD/2
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
MODE
CONTROL
REGISTERS
SCK
PAR/SER
SDI
VDD
GND
APPLICATIONS INFORMATION
Figure 2. Equivalent Input Circuit
CSAMPLE
3.5pF
RON
25
RON
25
VDD
LTC2262-12
AIN+
226212 F02
CSAMPLE
3.5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10
CONVERTER OPERATION
The LTC2262-12 is a low power 12-bit 150Msps A/D
converter that is powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially or single-ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise in
the system.) Many additional features can be chosen by
programming the mode control registers through a serial
SPI port. See the Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit(Figure2).Theinputsshouldbedrivendifferentially
around a common mode voltage set by the VCM output
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