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參數資料
| 型號： | LTC2259IUJ-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 16/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14-BIT 80MSPS 40-QFN |
| 產品培訓模塊： | LTC2262 - Ultra Low Power High Speed ADCs |
| 標準包裝： | 61 |
| 位數： | 14 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 并聯(lián)，串行，SPI |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 105mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-QFN（6x6） |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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23
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
TheLTC2261-14/LTC2260-14/LTC2259-14canalsophase
shift the CLKOUT+/CLKOUT– signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
Thecombinationofthesetwofeaturesenablesphaseshifts
of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
1
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
≤–1.000000V
0
1
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
applicaTions inForMaTion
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
226114 F14
ENC+
Figure 14. Phase Shifting CLKOUT
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LTC2259IUJ-14-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs |
| LTC2259IUJ-16 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259IUJ-16#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259IUJ-16#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259IUJ-16PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
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