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參數(shù)資料
型號(hào)： LTC2242IUP-10#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 26/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 250MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 10
采樣率（每秒）： 250M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 975mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
LTC2242-10
5
224210fd
power requireMenTs
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage
(Note 8)
●
2.375
2.5
2.625
V
PSLEEP
Sleep Mode Power
SHDN = High, OE = High, No CLK
1
mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
28
mW
LVDS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
●
2.375
2.5
2.625
V
IVDD
Analog Supply Current
●
285
320
mA
IOVDD
Output Supply Current
●
58
70
mA
PDISS
Power Dissipation
●
858
975
mW
CMOS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
●
0.5
2.5
2.625
V
IVDD
Analog Supply Current
(Note 7)
●
285
320
mA
PDISS
Power Dissipation
740
mW
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
TiMing characTerisTics The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Note 8)
●
1
250
MHz
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
1.9
1.5
2
500
ns
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
1.9
1.5
2
500
ns
tAP
Sample-and-Hold Aperture Delay
0.4
ns
tOE
Output Enable Delay
(Note 7)
●
5
10
ns
LVDS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1
1.7
2.8
ns
tC
ENC to CLKOUT Delay
(Note 7)
●
1
1.7
2.8
ns
DATA to CLKOUT Skew
(tC – tD) (Note 7)
●
–0.6
0
0.6
ns
Rise Time
0.5
ns
Fall Time
0.5
ns
Pipeline Latency
5
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1
1.7
2.8
ns
tC
ENC to CLKOUT Delay
(Note 7)
●
1
1.7
2.8
ns
DATA to CLKOUT Skew
(tC – tD) (Note 7)
●
–0.6
0
0.6
ns
Pipeline
Latency
Full Rate CMOS
5
Cycles
Demuxed Interleaved
5
Cycles
Demuxed Simultaneous
5 and 6
Cycles
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