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參數(shù)資料
| 型號： | LTC2224IUK#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 135MSPS SAMPL 48QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 135M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 680mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
LTC2224
5
2224fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage
●
3.1
3.3
3.5
V
OVDD
Output Supply Voltage
●
0.5
3.3
3.6
V
IVDD
Analog Supply Current
●
191
206
mA
PDISS
Power Dissipation
●
630
680
mW
PSHDN
Shutdown Power
SHDN = High, OE = High, No CLK
2
mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
35
mW
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
●
1
135
MHz
tL
ENC Low Time
Duty Cycle Stabilizer Off
●
3.5
3.7
500
ns
Duty Cycle Stabilizer On
●
2
3.7
500
ns
tH
ENC High Time
Duty Cycle Stabilizer Off
●
3.5
3.7
500
ns
Duty Cycle Stabilizer On
●
2
3.7
500
ns
tAP
Sample-and-Hold Aperture Delay
0
ns
tOE
Output Enable Delay
(Note 7)
●
510
ns
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.1
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
●
1.3
2.1
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
●
–0.6
0
0.6
ns
Pipeline Latency
5
Cycles
TI I G CHARACTERISTICS
U
W
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIRE E TS
W
U
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they will
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,
unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
straight line” fit to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive,
output CLOAD = 5pF.
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| LTC2224UK | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 135Msps ADC |
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