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參數(shù)資料
| 型號： | LTC2222IUK-11#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 11BIT 105MSPS SAMPL 48QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 535mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
LTC2222-11
18
222211f
APPLICATIO S I FOR ATIO
WU
UU
DIGITAL OUTPUTS
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, which
are isolated from the ADC power and ground. The addi-
tional N-channel transistor in the output driver allows
operation down to voltages as low as 0.5V. The internal
resistor in series with the output makes the output appear
as 50
to external circuitry and may eliminate the need for
external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2222-11 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 5pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs and improve the SNR.
Data Format
The LTC2222-11 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 1 shows the logic
states for the MODE pin.
222211 F12a
ENC–
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1
F
LTC2222-11
222211 F12b
ENC–
ENC+
130
3.3V
130
D0
Q0
MC100LVELT22
LTC2222-11
83
83
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Table 1. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
The converter is either overranged or underranged when
OF outputs a logic high.
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLOCKOUT. The CLOCKOUT pin can be
used to synchronize the converter data to the digital sys-
tem. This is necessary when using a sinusoidal encode. Data
will be updated just after CLOCKOUT rises and can be
latched on the falling edge of CLOCKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
LTC2222-11
222211 F13
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13. Digital Output Buffer
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2222UK | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit,105Msps/80Msps ADCs |
| LTC2222UK-11 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:11-Bit, 105Msps ADC |
| LTC2223 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit,105Msps/80Msps ADCs |
| LTC2223CUK | 功能描述:IC ADC 12BIT 80MSPS SAMPLE 48QFN RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2223CUK#PBF | 功能描述:IC ADC 12BIT 80MSPS SAMPLE 48QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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