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參數(shù)資料
| 型號： | LTC2220IUP-1#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 185MSPS 64-QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 185M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.18W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
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LTC2220-1
19
2220_1fa
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3VDD or 2/3VDD using external
resistors.
The lower limit of the LTC2220-1 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2220-1 is 1Msps.
Digital Output Modes
The LTC2220-1 can operate in several digital output modes:
LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3VDD, 2/3VDD or VDD. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logic values. Table 2 shows the logic states for the LVDS
pin.
APPLICATIO S I FOR ATIO
WU
UU
LTC2220-1
22201 F13a
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13a. Digital Output Buffer in CMOS Mode
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OVDD and OGND, which are isolated from the ADC
power and ground. The additional N-channel transistor in
the output driver allows operation down to voltages as low
as 0.5V. The internal resistor in series with the output
makes the output appear as 50
to external circuitry and
may eliminate the need for external damping resistors.
22201 F12a
ENC–
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1
F
LTC2220-1
22201 F12b
ENC–
ENC+
130
3.3V
130
D0
Q0
MC100LVELT22
LTC2220-1
83
83
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Table 2. LVDS Pin Function
LVDS
Digital Output Mode
GND
Full-Rate CMOS
1/3VDD
Demultiplexed CMOS, Simultaneous Update
2/3VDD
Demultiplexed CMOS, Interleaved Update
VDD
LVDS
DIGITAL OUTPUTS
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
D11 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
1111 1111 1111
0111 1111 1111
+0.999512V
0
1111 1111 1111
0111 1111 1111
+0.999024V
0
1111 1111 1110
0111 1111 1110
+0.000488V
0
1000 0000 0001
0000 0000 0001
0.000000V
0
1000 0000 0000
0000 0000 0000
–0.000488V
0
0111 1111 1111
1111 1111 1111
–0.000976V
0
0111 1111 1110
1111 1111 1110
–0.999512V
0
0000 0000 0001
1000 0000 0001
–1.000000V
0
0000 0000 0000
1000 0000 0000
<–1.000000V
1
0000 0000 0000
1000 0000 0000
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