參數(shù)資料
型號: LTC2208IUP
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 16-Bit, 130Msps ADC
中文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝: 9 X 9 MM, PLASTIC, MO-220-WNJR-5, QFN-64
文件頁數(shù): 6/32頁
文件大?。?/td> 1222K
代理商: LTC2208IUP
LTC2208
6
2208fa
POWER REQUIREW
range, otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 4)
U
The
denotes the specifications which apply over the full operating temperature
TIW
U
range, otherwise specifications are at T
A
= 25°C. (Note 4)
The
denotes the specifications which apply over the full operating temperature
SYMBOL
V
DD
P
SHDN
STANDARD LVDS OUTPUT MODE
OV
DD
I
VDD
I
OVDD
P
DIS
LOW POWER LVDS OUTPUT MODE
OV
DD
I
VDD
I
OVDD
P
DIS
CMOS OUTPUT MODE
OV
DD
I
VDD
P
DIS
PARAMETER
Analog Supply Voltage
Shutdown Power
CONDITIONS
(Note 8)
SHDN = V
DD
MIN
TYP
3.3
0.2
MAX
3.465
UNITS
3.135
V
mW
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power Dissipation
(Note 8)
3
3.3
380
74
1498
3.6
450
90
1782
V
mA
mA
mW
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power Dissipation
(Note 8)
3
3.3
380
31
1356
3.6
450
50
1650
V
mA
mA
mW
Output Supply Voltage
Analog Supply Current
Power Dissipation
(Note 8)
0.5
3.6
450
1485
V
380
1250
mA
mW
SYMBOL
f
S
t
L
t
H
t
AP
LVDS OUTPUT MODE (STANDARD and LOW POWER)
t
D
ENC to DATA Delay
t
C
ENC to CLKOUT Delay
t
SKEW
DATA to CLKOUT Skew
t
RISE
Output Rise Time
t
FALL
Output Fall Time
Data Latency
Data Latency
CMOS OUTPUT MODE
t
D
ENC to DATA Delay
t
C
ENC to CLKOUT Delay
t
SKEW
DATA to CLKOUT Skew
Data Latency
Data Latency
PARAMETER
Sampling Frequency
ENC Low Time
ENC High Time
Sample-and-Hold Aperture Delay
CONDITIONS
(Note 8)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
MIN
1
3.65
2.6
3.65
2.6
TYP
3.846
3.846
3.846
3.846
–1
MAX
130
1000
1000
1000
1000
UNITS
MHz
ns
ns
ns
ns
ns
(Note 7)
(Note 7)
(t
C
-t
D
) (Note 7)
1.3
1.3
–0.6
2.5
2.5
0
0.5
0.5
7
3.8
3.8
0.6
ns
ns
ns
ns
ns
Cycles
(Note 7)
(Note 7)
(t
C
-t
D
) (Note 7)
Full Rate CMOS
Demuxed
1.3
1.3
–0.6
2.7
2.7
0
7
7
4.0
4.0
0.6
ns
ns
ns
Cycles
Cycles
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