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參數(shù)資料
| 型號(hào)： | LTC2207-14 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 14-Bit, 105Msps/80Msps ADCs |
| 中文描述： | 14位，105Msps/80Msps模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 1298K |
| 代理商： | LTC2207-14 |
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LTC2207-14/LTC2206-14
16
220714614fa
CONVERTER OPERATION
The LTC2207-14/LTC2206-14 are CMOS pipelined
multistep converters with a front-end PGA. As
shown in Figure 1, the converter has five pipelined
ADC stages; a sampled analog input will result in
a digitized value seven clock cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2207-14/LTC2206-14 have two phases of
operation, determined by the state of the differential
ENC
+
/ENC
–
input pins. For brevity, the text will refer to
ENC
+
greater than ENC
–
as ENC high and ENC
+
less than
ENC
–
as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden-
tical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fifth
stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
OPERATION
(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is
defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC
+
equals the ENC
–
voltage
to the instant that the input signal is held by the sample-
and-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2
π
f
IN
t
JITTER
)
APPLICATIONS INFORMATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2207CUK-14 | 14-Bit, 105Msps/80Msps ADCs |
| LTC2207IUK-14 | 14-Bit, 105Msps/80Msps ADCs |
| LTC2207UK-14 | 14-Bit, 105Msps/80Msps ADCs |
| LTC2206 | 16-Bit, 105Msps/80Msps ADCs |
| LTC2206CUK | 16-Bit, 105Msps/80Msps ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2207CUK | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP |
| LTC2207CUK#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 105MSPS 48-QFN 制造商:Linear Technology 功能描述:IC ADC 16BIT 105MSPS QFN-48 制造商:Linear Technology 功能描述:ADC 16BIT 105MSPS 48QFN 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 105MSPS, QFN-48; Resolution (Bits):16bit; Sampling Rate:105MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:273mA; Digital IC Case Style:QFN; No. of Pins:48 ;RoHS Compliant: Yes |
| LTC2207CUK#PBF | 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 105MSPS, QFN-48 |
| LTC2207CUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 105MSPS 48-QFN |
| LTC2207CUK-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 105Msps/80Msps ADCs |
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