參數(shù)資料
型號(hào): LTC2205CUK-14#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 1/28頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 65MSPS 48-QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 776mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
LTC2205-14
1
220514fb
14-Bit, 65Msps ADC
The LTC2205-14 is a sampling 14-bit A/D converter
designed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2205-14 is perfect for demanding communications
applications, with AC performance that includes 78.3dB
SNR and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 90fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±1LSB DNL
(no missing codes).
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENCinputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
n Telecommunications
n Receivers
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
n ATE
n Sample Rate: 65Msps
n 78.3dB SNR and 98dB SFDR (2.25VP-P Range)
n SFDR >90dB at 140MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Optional Data Output Randomizer
n Single 3.3V Supply
n Power Dissipation: 600mW
n Optional Clock Duty Cycle Stabilizer
n Out-of-Range Indicator
n Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit)
40Msps: LTC2204 (16-Bit)
n 48-Pin (7mm × 7mm) QFN Package
LTC2205-14: 32K Point FFT,
fIN = 5.1MHz, –1dBFS,
PGA = 0, DITH = 0
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D13
D0
ENC
PGA
SHDN
DITH
MODE
OE
RAND
ENC
VCM
ANALOG
INPUT
220514 TA01
0.5V TO 3.6V
3.3V
SENSE
OGND
OVDD
2.2μF
0.1μF
VDD
GND
ADC CONTROL INPUTS
AIN+
AIN
OF
CLKOUT
0.1μF
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FREQUENCY (MHz)
0
AMPLITUDE
(dBFS)
–80
–20
–10
0
10
20
25
220514 G04
–100
–110
–120
–40
–60
–90
–30
–130
–50
–70
515
30
FEATURES
DESCRIPTION
APPLICATIONS
TYPICAL APPLICATION
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