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參數(shù)資料
| 型號： | LTC2153CUJ-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DUAL 310MSPS 40QFN |
| 標(biāo)準(zhǔn)包裝： | 61 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 310M |
| 數(shù)據(jù)接口： | 并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 479mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-QFN（6x6） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分 |
| 配用： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
LTC2153-14
14
215314f
applicaTions inForMaTion
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 3). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100 termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100 termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
When CLKINV is set to 0 in the SPI register A2, the OF
signal is valid when CLKOUT+ is low, as shown in the
Timing Diagrams section.
Phase Shifting the Output Clock
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
trol register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 11).
Figure 11. Phase Shifting CLKOUT
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
215314 F11
ENC+
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2153IUJ-12#PBF | 制造商:Linear Technology 功能描述:IC ADC 12BIT DUAL 310MSPS 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 310Msps, 1.8V ADC, DDR LVDS Outputs |
| LTC2153IUJ-12#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 12BIT DUAL 310MSPS 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 310Msps, 1.8V ADC, DDR LVDS Outputs |
| LTC2153IUJ-14#PBF | 功能描述:IC ADC 14BIT DUAL 310MSPS 40QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| LTC2153IUJ-14#TRPBF | 功能描述:IC ADC 14BIT DUAL 310MSPS 40QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| LTC2155-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit 250Msps |
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