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| 型號： | LTC1968IMS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 296K |
| 描述： | IC CONVERTER RMS-DC PREC 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 電流 - 電源： | 2.3mA |
| 電源電壓： | 5.0V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
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LTC1968
1968f
APPLICATIO S I FOR ATIO
U
U
U
somewhat lower (H0.7 " 1.27 H 0.9Hz) than with 10礔
alone. To adjust the bandwidth of either of them, simply
scale all the capacitors by a common multiple, and leave
the resistors unchanged.
The step responses of the LTC1968 with 10礔-only and
with the two post filters are shown in Figure 14. This is the
rising edge RMS output response to a 10Hz input starting
at t = 0. Although the falling edge response is the worst
case for settling, the rising edge illustrates the ripple that
these post filters are designed to address, so the rising
edge makes for a better intuitive comparison.
The initial rise of the LTC1968 will have enhanced slew rates
with DC and very low frequency inputs due to saturation
effects in the ?modulator. This is seen in Figure 14 in two
ways. First, the 10礔-only output is seen to rise very quickly
in the first 40ms. The second way this effect shows up is
that the post filter outputs have a modest overshoot, on the
order of 3mV to 4mV, or 3% to 4%. This is only an issue
with input frequency bursts at 50Hz or less, and even with
the overshoot, the settling to a given level of accuracy
improves due to the initial speedup.
As predicted by Figure 6, the DC error with 10礔 is well
under 1mV and is not noticeable at this scale. However, as
predicted by Figure 8, the peak error with the ripple from
a 10Hz input is much larger, in this case about 5mV. As can
be clearly seen, the post filters reduce this ripple. Even the
wider bandwidth of Figure 12s filter is seen to cut the
ripple down substantially (to <1mV) while the settling to
1% happens faster. With the narrower bandwidth of Figure
14s filter, the step response is somewhat slower, but the
double frequency output ripple is just 150礦.
Figure 15 shows the step response of the same three cases
with a burst of 60Hz rather than 10Hz. With 60Hz, the initial
portion of the step response is free of the boost seen in
Figure 14 and the two post-filter responses have less than
1% overshoot. The 10礔-only case still has noticeable
120Hz ripple, but both filters have removed all detectable
ripple on this scale. This is to be expected; the first order
filter will reduce the ripple about 6:1 for a 6:1 change in
frequency, while the third order filters will reduce the
ripple about 6
3
:1 or 216:1 for a 6:1 change in frequency.
Again, the two filter topologies have the same relative
shape, so the step response and ripple filtering trade-offs
of the two are the same, with the same performance of
each possible with the other by scaling it accordingly.
Figures 16 and 17 show the peak error vs. frequency for a
selection of capacitors for the two different filter topolo-
gies. To keep the clean step response, scale all three
capacitors within the filter. Scaling the buffered topology
of Figure 12 is simple because the capacitors are in a
10:1:10 ratio. Scaling the DC accurate topology of Figure
14 can be done with standard value capacitors; one decade
of scaling is shown in Table 2.
Table 2: One Decade of Capacitor Scaling for Figure 13 with EIA
Standard Values
C
AVE
C
1
= C
2
=
1礔
0.22礔
1.5礔
0.33礔
2.2礔
0.47礔
3.3礔
0.68礔
4.7礔
1礔
6.8礔
1.5礔
Figure 15. Step Responses with 60Hz Burst
Figure 14. Step Responses with 10Hz Burst
INPUT
BURST
200mV/
DIV
20mV/
DIV
10礔 ONLY
FIGURE 12
FIGURE 13
STEP
RESPONSE
100ms/DIV
1968 F14
INPUT
BURST
200mV/
DIV
20mV/
DIV
0礔 ONLY
FIGURE 12
FIGURE 13
STEP
RESPONSE
100ms/DIV
1968 F15
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