參數(shù)資料
型號: LTC1955IUH
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32
封裝: 5 X 5 MM, 0.75 MM HEIGHT, MO-220WHHD, QFN-32
文件頁數(shù): 6/20頁
文件大?。?/td> 243K
代理商: LTC1955IUH
LTC1955
14
1955fb
10kV ESD Protection
All smart card pins (CLK A/CLK B, RST A/RST B, I/O A/I/O B,
C4A, C8A and VCCA/VCCB) can withstand over 10kV of
human body model ESD in-situ. In order to ensure proper
ESD protection, careful board layout is required. The
PGND and SGND pins should be tied directly to a ground
plane. The VCCA/VCCB capacitors should be located very
close to the VCCA/VCCB pins and tied immediately to the
ground plane.
Capacitor Selection
Warning: A polarized capacitor such as tantalum or alumi-
num should never be used for the ying capacitor since
its voltage can reverse upon start-up of the LTC1955.
Low ESR ceramic capacitors should always be used for
the ying capacitor.
A total of six capacitors are required to operate the LTC1955.
An input bypass capacitor is required at PVBATT, SVBATT
and DVCC. Output bypass capacitors are required on each
of the smart card VCCA/VCCB pins. A charge pump ying
capacitor is required from C+ to Cand a charge storage
capacitor is required on the charge pump out pin CPO.
To prevent excessive noise spikes due to charge pump
operation, low ESR (equivalent series resistance) multi-
layer ceramic capacitors are strongly recommended.
There are several types of ceramic capacitors available, each
having considerably different characteristics. For example,
X7R/X5R ceramic capacitors have excellent voltage and
temperature stability but relatively low packing density.
Y5V ceramic capacitors have apparently higher packing
density but poor performance over their rated voltage or
temperature ranges. Under certain voltage and temperature
conditions, Y5V and X7R/X5R ceramic capacitors can be
compared directly by case size rather than specied value
for a desired minimum capacitance.
Placement of the capacitors is critical for correct operation
of the LTC1955. Because the charge pump generates large
current steps, all of the capacitors should be placed as close
to the LTC1955 as possible. The low impedance nature of
multilayer ceramic chip capacitors will minimize voltage
spikes but only if the power path is kept very short (i.e.,
minimum inductance). The PVBATT/SVBATT nodes should
APPLICATIONS INFORMATION
be especially well bypassed. The capacitor for this node
should be directly adjacent to the QFN package. The CPO
and ying capacitors should be very close as well. The
LTC1955 can tolerate more distance between the LDO
capacitors and the VCCA/B pins.
Figure 3 shows an example of a tight printed circuit
board using single-layer copper. For best performance, a
multilayer board can be used and should employ a solid
ground plane on at least one layer.
The following capacitors are recommended for use with
the LTC1955.
TYPE
VALUE
CASE SIZE MURATA P/N
CIN
CPO
X5R
4.7μF
0805
GRM40-034 X5R 475K 6.3
CFLY
VCCA/B
X5R
1μF
0603
GRM39 X5R 105K 6.3
CDVCC
X5R
0.1μF
0402
GRM36 X5R 104K 10
Figure 3. Optimum Single-Layer PCB Layout
VCCA
GND
VBATT
VCCB 1955 F03
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