參數(shù)資料
型號(hào): LTC1871HMS
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.05 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO10
封裝: PLASTIC, MSOP-10
文件頁(yè)數(shù): 34/36頁(yè)
文件大?。?/td> 519K
代理商: LTC1871HMS
LTC1871
7
1871fe
PIN FUNCTIONS
RUN (Pin 1): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro-
gramming the start-up threshold for the converter. The
falling RUN pin threshold is nominally 1.248V and the
comparator has 100mV of hysteresis for noise immunity.
When the RUN pin is below this input threshold, the IC
is shut down and the VIN supply current is kept to a low
value (typ 10μA). The Absolute Maximum Rating for the
voltage on this pin is 7V.
ITH (Pin 2): Error Amplier Compensation Pin. The
current comparator input threshold increases with this
control voltage. Nominal voltage range for this pin is 0V
to 1.40V.
FB (Pin 3): Receives the feedback voltage from the external
resistor divider across the output. Nominal voltage for
this pin in regulation is 1.230V.
FREQ (Pin 4): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nominal
voltage at the FREQ pin is 0.6V.
MODE/SYNC (Pin 5): This input controls the operating
mode of the converter and allows for synchronizing the
operating frequency to an external clock. If the MODE/
SYNC pin is connected to ground, Burst Mode operation
is enabled. If the MODE/SYNC pin is connected to INTVCC,
or if an external logic-level synchronization signal is ap-
plied to this input, Burst Mode operation is disabled and
the IC operates in a continuous mode.
GND (Pin 6): Ground Pin.
GATE (Pin 7): Gate Driver Output.
INTVCC (Pin 8): The Internal 5.20V Regulator Output.
The gate driver and control circuits are powered from
this voltage. Decouple this pin locally to the IC ground
with a minimum of 4.7μF low ESR tantalum or ceramic
capacitor.
VIN (Pin 9): Main Supply Pin. Must be closely decoupled
to ground.
SENSE (Pin 10): The Current Sense Input for the Control
Loop. Connect this pin to the drain of the power MOSFET
for VDS sensing and highest efciency. Alternatively, the
SENSE pin may be connected to a resistor in the source
of the power MOSFET. Internal leading edge blanking is
provided for both sensing methods.
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