參數(shù)資料
型號： LTC1850
廠商： Linear Technology Corporation
元件分類： ADC
英文描述： 8-Channel, 10-Bit/12-Bit, 1.25Msps Sampling ADCs
中文描述： 8通道，10-Bit/12-Bit，1.25MSPS時采樣ADC
文件頁數(shù)： 1/28頁
文件大小： 283K
代理商： LTC1850
1
LTC1850/LTC1851
8-Channel, 10-Bit/12-Bit,
1.25Msps Sampling ADCs
DESCRIPTIOU
18501f
The 10-bit LTC
1850 and 12-bit LTC1851 are complete
8-channel data acquisition systems. They include a flex-
ible 8-channel multiplexer, a 1.25Msps successive approxi-
mation analog-to-digital converter with sample-and-hold,
an internal 2.5V reference and reference buffer amplifier,
and a parallel output interface. The multiplexer can be con-
figured for single-ended or differential inputs, two gain
ranges and unipolar or bipolar operation.
The ADCs have a scan mode that will repeatedly cycle
through all 8 multiplexer channels and can also be
programmed with a sequence of up to 16 addresses and
configurations that can be scanned in succession. The
sequence memory can also be read back. The reference
and buffer amplifier provide pin strappable ranges of
4.096V, 2.5V and 2.048V. The parallel output includes
the 10-bit or 12-bit conversion result plus the 4-bit
multiplexer address. The digital outputs are powered
from a separate supply allowing for easy interface to 3V
digital logic. Typical power consumption is 40mW at
1.25Msps from a single 5V supply.
, LTC and LT are registered trademarks of Linear Technology Corporation.
I
Flexible 8-Channel Multiplexer
I
Single-Ended or Differential Inputs
I
Two Gain Ranges Plus Unipolar and Bipolar
Operation
I
1.25Msps Sampling Rate
I
Single 5V Supply and 40mW Power Dissipation
I
Scan Mode and Programmable Sequencer
I
Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851
I
True Differential Inputs Reject Common Mode Noise
I
Internal 2.5V Reference
I
Parallel Output Includes MUX Address
I
Easy Interface to 3V Logic
I
Nap and Sleep Shutdown Modes
APPLICATIU
I
High Speed Data Acquisition
I
Test and Measurement
I
Imaging Systems
I
Telecommunications
I
Industrial Process Control
I
Spectrum Analysis
FEATURES
BLOCK DIAGRA
BUSY
DIFF
OUT
/S6
A2
OUT
/S5
A1
OUT
/S4
A0
/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
1851 BD
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OUTPUT
DRIVERS
DATA
LATCHES
OV
DD
REF AMP
REFCOMP
REFIN
REFOUT
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
8-CHANNEL
MULTIPLEXER
2.5V
REFERENCE
INTERNAL
CLOCK
LTC1851
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
12-BIT
1.25Msps ADC
CODE
0
–1.00
I
–0.50
0.00
0.50
1.00
512 1024 1536 2048
LTC1850/51 G01
2560 3072 3584 4096
Integral Linearity, LTC1851
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