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參數(shù)資料
| 型號(hào)： | LTC1799IS5#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 33MHZ TSOT23-5 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 1kHz ~ 33MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 7mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | SOT-23-5 細(xì)型，TSOT-23-5 |
| 包裝： | 帶卷 (TR) |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-5 |
| 安裝類型： | 表面貼裝 |
LTC1799
6
1799fc
Theory oF operaTion
As shown in the Block Diagram, the LTC1799’s master
oscillator is controlled by the ratio of the voltage between
the V+ and SET pins and the current entering the SET pin
(IRES).ThevoltageontheSETpinisforcedtoapproximately
1.13V below V+ by the PMOS transistor and its gate bias
voltage. This voltage is accurate to ±7% at a particular
input current and supply voltage (see Figure 1). The ef-
fective input resistance is approximately 2k.
A resistor RSET, connected between the V+ and SET pins,
“l(fā)ocks together” the voltage (V+ – VSET) and current, IRES,
variation. This provides the LTC1799’s high precision. The
master oscillation frequency reduces to:
MO =10MHz
10k
RSET
The LTC1799 is optimized for use with resistors between
10kand200k,correspondingtomasteroscillatorfrequen-
ciesbetween0.5MHzand10MHz.Accuratefrequenciesup
to 20MHz (RSET = 5k) are attainable if the supply voltage
is greater than 4V.
Toextendtheoutputfrequencyrange,themasteroscillator
signal may be divided by 1, 10 or 100 before driving OUT
Figure 2. RSET vs Desired Output Frequency
(Pin 5). The divide-by value is determined by the state of
the DIV input (Pin 4). Tie DIV to GND or drive it below 0.5V
to select ÷1. This is the highest frequency range, with the
master output frequency passed directly to OUT. The DIV
pin may be floated or driven to midsupply to select ÷10,
the intermediate frequency range. The lowest frequency
range, ÷100, is selected by tying DIV to V+ or driving it to
within 0.4V of V+. Figure 2 shows the relationship between
RSET, divider setting and output frequency, including the
overlapping frequency ranges near 100kHz and 1MHz.
The CMOS output driver has an on resistance that is typi-
cally less than 100Ω. In the ÷1 (high frequency) mode,
the rise and fall times are typically 7ns with a 5V supply
and 11ns with a 3V supply. These times maintain a clean
square wave at 10MHz (20MHz at 5V supply). In the ÷10
and÷100modes,wheretheoutputfrequencyismuchlower,
slew rate control circuitry in the output driver increases
the rise/fall times to typically 14ns for a 5V supply and
19ns for a 3V supply. The reduced slew rate lowers EMI
(electromagnetic interference) and supply bounce.
Figure 1. V+ – VSET Variation with IRES
IRES (A)
1
0.8
V RES
=
V
+ –
V
SET
1.2
1.3
1.4
10
100
1000
1799 F01
1.1
1.0
0.9
V+ = 5V
V+ = 3V
TA = 25°C
DESIRED OUTPUT FREQUENCY (Hz)
10
R
SET
(k)
100
1k
100k
1M
10M
1799 F02
1
10k
1000
100M
÷100
÷10
÷1
MOST
ACCURATE
OPERATION
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