參數(shù)資料
型號(hào)： LTC1753CSW
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 10-Bit D-Type Transparent Read-Back Latches 24-SOIC 0 to 70
中文描述： SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO20
封裝： 0.300 INCH, PLASTIC, SO-20
文件頁(yè)數(shù)： 7/24頁(yè)
文件大小： 269K
代理商： LTC1753CSW
7
LTC1753
COMP (Pin 10):
External Compensation. The COMP pin is
connected directly to the output of the error amplifier and
the input of the PWM comparator. An RC+C network is
used at this node to compensate the feedback loop to
provide optimum transient response.
V
FB
(Pin 11):
Voltage Feedback. V
FB
is the tap point of the
internal resistor divider connected from SENSE to SGND.
During rapid and heavy output loading conditions, a small
capacitor between the SENSE and V
FB
pin creates a feed-
forward path that reduces the transient recovery time. For
applications where extremely low output ripple is re-
quired, low ESR capacitors are typically used. In this case,
a small capacitor between SENSE and V
FB
helps to com-
pensate the switching loop. This pin can be left floating,
but should be isolated from high current switching nodes.
FAULT (Pin 12):
Overvoltage Fault. FAULT is an open-
drain output. If V
OUT
reaches 13% above the nominal
output voltage, FAULT will go low and G1 and G2 will be
disabled. Once triggered, the LTC1753 will remain in this
state until the power supply is recycled or the OUTEN pin
is toggled. If OUTEN = 0, FAULT floats or is pulled high by
an external resistor.
PWRGD (Pin 13):
Power Good. This is an open-drain
signal to indicate validity of output voltage. A high indi-
cates that the output has settled to within
±
3% of the rated
output for more than 1ms. PWRGD will go low if the output
is out of regulation for more than 500
μ
s. If OUTEN = 0,
PWRGD pulls low.
VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14):
Digital Voltage Select. TTL inputs used to set the regulated
output voltage required by the processor (Table 2). There
is an internal 20k
pull-up at each pin. When all five VID
n
pins are high or floating, the chip will shut down.
OUTEN (Pin 19):
Output Enable. TTL input which enables
the output voltage. The external MOSFET temperature can
be monitored with an external thermistor as shown in
Figure 11. When the OUTEN input voltage drops below
1.7V, the drivers are internally disabled to prevent the
MOSFETs from heating further. If OUTEN is less than 1.2V
for longer than 30
μ
s, the LTC1753 will enter shutdown
mode. The internal oscillator can be synchronized to a
faster external clock by applying the external clocking
signal to the OUTEN pin. (See Applications Information.)
G1 (Pin 20):
Gate Drive for the Upper N-Channel MOSFET,
Q1. This output will swing from PV
CC
to GND. It will always
be low when G2 is high or the output is disabled.
PIU
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