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參數(shù)資料
| 型號： | LTC1751-3.3 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Micropower, Regulated Charge Pump DC/DC Converters |
| 中文描述： | 微功耗，穩(wěn)壓電荷泵DC / DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 211K |
| 代理商： | LTC1751-3.3 |
7
LTC1751/LTC1751-3.3/LTC1751-5
APPLICATIOU
Operation (Refer to Simplified Block Diagrams)
The LTC1751 family uses a switched capacitor charge
pump to boost V
IN
to a regulated output voltage. Regula-
tion is achieved by sensing the output voltage through a
resistor divider and enabling the charge pump when the
divided output drops below the lower trip point of COMP1.
When the charge pump is enabled, a 2-phase
nonoverlapping clock activates the charge pump switches.
The flying capacitor is charged to V
IN
on phase 1 of the
clock. On phase 2 of the clock, it is stacked in series with
V
IN
and connected to V
OUT
. This sequence of charging and
discharging the flying capacitor continues at the clock
frequency until the divided output voltage reaches the
upper trip point of COMP1. Once this happens the charge
pump is disabled. When the charge pump is disabled the
device typically draws less than 20
μ
A from V
IN
thus
providing high efficiency under low load conditions.
In shutdown mode all circuitry is turned off and the
LTC1751 draws only leakage current from the V
IN
supply.
Furthermore, V
OUT
is disconnected from V
IN
. The SHDN
pin is a CMOS input with a threshold voltage of approxi-
mately 0.8V. The LTC1751 is in shutdown when a logic low
is applied to the SHDN pin. The quiescent supply current
of the LTC1751 will be slightly higher if the SHDN pin is
driven high with a voltage that is below V
IN
than if it is
driven all the way to V
IN
. Since the SHDN pin is a high
impedance CMOS input it should never be allowed to float.
To ensure that its state is defined it must always be driven
with a valid logic level.
W
U
U
Power Efficiency
The efficiency (
η
) of the LTC1751 family is similar to that
of a linear regulator with an effective input voltage of twice
the actual input voltage. This occurs because the input
current for a voltage doubling charge pump is approxi-
mately twice the output current. In an ideal regulated
doubler the power efficiency would be given by:
η=
=
=
P
P
V
V
I
I
V
2
V
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
2
At moderate to high output power, the switching losses
and quiescent current of the LTC1751 are negligible and
the expression is valid. For example, an LTC1751-5 with
V
IN
= 3V, I
OUT
= 50mA and V
OUT
regulating to 5V, has a
measured efficiency of 82% which is in close agreement
with the theoretical 83.3% calculation. The LTC1751 prod-
uct family continues to maintain good efficiency even at
fairly light loads because of its inherently low power
design.
Short-Circuit/Thermal Protection
During short-circuit conditions, the LTC1751 will draw
between 200mA and 400mA from V
IN
causing a rise in the
junction temperature. On-chip thermal shutdown circuitry
disables the charge pump once the junction temperature
exceeds approximately 160
°
C and re-enables the charge
pump once the junction temperature drops back to ap-
proximately 150
°
C. The device will cycle in and out of
thermal shutdown indefinitely without latchup or damage
until the short circuit on V
OUT
is removed.
V
IN
, V
OUT
Capacitor Selection
The style and value of capacitors used with the LTC1751
family determine several important parameters such as
output ripple, charge pump strength and minimum
start-up time.
To reduce noise and ripple, it is recommended that low
ESR (<0.1
) capacitors be used for both C
IN
and C
OUT
.
These capacitors should be either ceramic or tantalum and
should be 6.8
μ
F or greater. Aluminum capacitors are not
recommended because of their high ESR. If the source
impedance to V
IN
is very low, up to several megahertz, C
IN
may not be needed. Alternatively, a somewhat smaller
value of input capacitor may be adequate, but will not be
as effective in preventing ripple on the V
IN
pin.
The value of C
OUT
controls the amount of output ripple.
Increasing the size of C
OUT
to 10
μ
F or greater will reduce
the output ripple at the expense of higher minimum turn on
time and higher start-up current. See the section Output
Ripple.
相關PDF資料 |
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|---|---|
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| LTC1753CSW | 10-Bit D-Type Transparent Read-Back Latches 24-SOIC 0 to 70 |
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| LTC1755 | 10-Bit D-Type Transparent Read-Back Latches 24-PDIP 0 to 70 |
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