±1V. VDD selects ±1." />
參數(shù)資料
型號(hào): LTC1744CFW
廠商: Linear Technology
文件頁(yè)數(shù): 24/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 50MSPS 48-TSSOP
標(biāo)準(zhǔn)包裝: 39
位數(shù): 14
采樣率(每秒): 50M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.5W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
9
LTC1744
1744f
SENSE (Pin 1): Reference Sense Pin. Ground selects
±1V. VDD selects ±1.6V. Greater than 1V and less than
1.6V applied to the SENSE pin selects an input range of
±VSENSE, ±1.6V is the largest valid input range.
VCM (Pin 2): 2.5V Output and Input Common Mode Bias.
Bypass to ground with 4.7
F ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC
Power Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND
with 1
F ceramic chip capacitor.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with
0.1
F ceramic chip capacitor. Do not connect to Pin 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with
0.1
Fceramicchipcapacitor,toPin14witha4.7Fceramic
capacitor and to ground with 1
F ceramic capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with
0.1
Fceramicchipcapacitor,toPin11witha4.7Fceramic
capacitor and to ground with 1
F ceramic capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with
0.1
F ceramic chip capacitor. Do not connect to Pin 11.
PI FU CTIO S
UU
U
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on
the positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1
F
ceramic for single-ended encode signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs. D0 is the LSB.
OVDD (Pins 32, 43): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
F ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs. D13 is the MSB.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(Note 5)
FREQUENCY (MHz)
0
AMPLITUDE
(dB) –60
–30
0.5
–10
–20
–40
–50
–70
–80
–100
–110
–130
–140
816
24.99
1744 G36
–90
–120
–150
246
10 12 14
18 20 22 24
TA = 25°C
FREQUENCY (MHz)
0
AMPLITUDE
(dB) –60
–30
0.5
–10
–20
–40
–50
–70
–80
–100
–110
–130
–140
816
24.99
1744 G37
–90
–120
–150
246
10 12 14
18 20 22 24
TA = 25°C
Input = 5MHz, –25dBFS, No Dither
Input = 5MHz, –25dBFS,
Dither Applied
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