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參數(shù)資料
| 型號： | LTC1699-81 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | SMBus VID Voltage Programmers(SMBus接口 VID電壓編程器) |
| 中文描述： | VID電壓編程的SMBus（西元的SMBus接口電壓編程器） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 250K |
| 代理商： | LTC1699-81 |
LTC1699 Series
15
APPLICATIU
W
U
U
Operating Sequence
A typical control sequence for the LTC1699-80,
LTC1699-81 and LTC1699-82 is as follows:
On power up, the DCON bit is preset to a high state by
the power-on reset (POR) circuit. The CPU_ON, IO_ON
and CLK_ON pins are pulled low to shut down the DC/
DC converters. PGOOD pulls low to indicate that the
converters are not in regulation.
Pull VRON low as a precaution. Take SEL high or low to
select the divider setting; e.g., one that suits the existing
power source (battery or wall-pack).
Use the Setup protocol to load the appropriate divider
settings in Registers 0 and 1 and enable the on/off state
machine.
Use the Read-Back protocol to verify the contents of
Registers 0 and 1.
Repeat the setup and read-back if the codes are incor-
rect (due to bus conflicts).
Send two On protocols in succession to clear the DCON
bit.
Use the Read-Back protocol to verify that the DCON is
low. A high state will indicate that an On command code
was corrupted by bus conflicts.
Pull VRON high. Since DCON = 0, the CPU_ON, IO_ON
and CLK_ON pins enter a high impedance state, allow-
ing the DC/DC converters to soft-start. PGOOD stays
low for 50
μ
s.
To shut down the supply, send two Off protocols to set
the DCON bit high or pull VRON low if immediate
shutdown is required.
The VRON signal in the 8-pin MSOP versions of the
LTC1699-80, LTC1699-81 and LTC1699-82 are pulled
high internally by a 2.5
μ
A current source. For these
versions, the converters are turned on or off only through
the SMBus interface.
Overvoltage Protection Faults
Toggling the SEL pin, i.e. changing the ladder setting “on
the fly” can trigger some converters with over-voltage
fault protection (OVP) into a fault state if the new setting
calls for a lower output voltage. For some converters such
as the LTC1702, cycling the power supply is the only way
to clear the fault and restore normal operation.
For the LTC1702, an OVP fault is triggered if the difference
between the programmed and prevailing output voltages
is greater than 15%, and persists for more than 25
μ
s. To
prevent the OVP fault from disabling the LTC1702, tie the
FAULT pin of the LTC1702 low. Tying FAULT low does not
disable the OVP circuit but blocks its effects.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1699-82 | SMBus VID Voltage Programmers(SMBus 接口VID電壓編程器) |
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| LTC1701ES5 | Synchronous 8-Bit Up/Down Binary Counters 24-SOIC 0 to 70 |
| LTC1703 | Synchronous 8-Bit Up/Down Binary Counters 24-PDIP 0 to 70 |
| LTC1703CG | Synchronous 8-Bit Up/Down Binary Counters 24-PDIP 0 to 70 |
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