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| 型號(hào)： | LTC1668 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit, 50Msps Differential Current OutputDAC(16位，50Msps，差分電流輸出數(shù)模轉(zhuǎn)換器) |
| 中文描述： | 16位，50 MSPS的差分電流OutputDAC（16位，50 MSPS的，差分電流輸出數(shù)模轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大小： | 732K |
| 代理商： | LTC1668 |
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7
LTC1668
APPLICATIOU
Substituting the values found earlier for I
OUT A
, I
OUT B
and
I
OUTFS
:
V
DIFF
= {2 DAC Code – 65535)/65536} 8
(R
LOAD
/R
SET
) (V
REF
)
From these equations some of the advantages of differen-
tial mode operation can be seen. First, any common mode
noise or error on I
OUT A
and I
OUT B
is cancelled. Second, the
signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times I
OUT A
and
I
OUT B
, such as reference or I
OUTFS
noise, cancel near
midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.
Note that the term (R
LOAD
/R
SET
) appears in both the
differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
R
LOAD
to R
SET
, and the Gain Error tempco is affected by the
temperature tracking of R
LOAD
with R
SET
. Note also that
the absolute tempco of R
LOAD
is very critical for DC
nonlinearity. As the DAC output changes from 0mA to
10mA the R
LOAD
resistor will heat up slightly, and even a
very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.
W
U
U
(7)
Analog Outputs
The LTC1668 has two complementary current outputs,
I
OUT A
and I
OUT B
(see DAC Transfer Function). The output
impedance of I
OUT A
and I
OUT B
(R
IOUT A
and R
IOUT B
) is
typically 1.1k
to LADCOM. (See the Equivalent Analog
Output Circuit, Figure 1.) The LADCOM pin is the com-
mon connection for the internal DAC attenuator ladder. It
usually is tied to analog ground, but more generally it
should connect to the same potential as the lead resistors
on I
OUT A
and I
OUT B
. The LADCOM pin carries a constant
current to V
SS
of approximately 0.32 (I
OUTFS
), plus any
current that flows from I
OUT A
and I
OUT B
through the
R
IOUT A
and R
IOUT B
resistors.
The specified output compliance voltage range is
±
1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I
OUT A
into the virtual ground of an
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below –1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than
±
0.5V
P-P
on I
OUT A
and
I
OUT B
due to nonlinear capacitance and other large-signal
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
The LTC1668 is specified to operate with full-scale output
current, I
OUTFS
, from the nominal 10mA down to 1mA.
This can be useful to reduce power dissipation or to adjust
full-scale value. However, that the LTC1668 DC and AC
accuracy is specified only at I
OUTFS
= 10mA, and DC and
AC accuracy will fall off significantly at lower I
OUTFS
values.
At I
OUTFS
= 1mA, INL and DNL typically degrade to the 14-
bit to 13-bit level, compared to 16-bit to 15-bit typical
accuracy at 10mA I
OUTFS
. Increasing I
OUTFS
from 1mA, the
20
19
23
18
R
IOUT B
1.1k
5pF
LTC1668
5pF
–5V
1668 F01
R
IOUT A
1.1k
LADCOM
I
OUT A
I
OUT B
V
SS
52.3
52.3
Figure 1. Equivalent Analog Output Circuit
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