參數(shù)資料
型號(hào)： LTC1628IG-SYNC#TR
廠(chǎng)商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： 3 A SWITCHING CONTROLLER, 360 kHz SWITCHING FREQ-MAX, PDSO28
封裝： 0.209 INCH, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 658K
代理商： LTC1628IG-SYNC#TR
21
LTC1628-SYNC
1628syncfa
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range,
fH, is equal to the capture range, fC:
fH = fC = ±0.5 fO (150kHz-300kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency f0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor CLP holds the voltage. The
LTC1628-SYNC PLLIN pin must be driven from a low
impedance source such as a logic gate located close to the
pin. When using multiple LTC1628-SYNC’s (or LTC1629’s,
as shown in Figure 14) for a phase-locked system, the
PLLFLTR pin of the master oscillator should be biased at
a voltage that will guarantee the slave oscillator(s) ability
to lock onto the master’s frequency. A DC voltage of 0.7V
to 1.7V applied to the master oscillator’s PLLFLTR pin is
recommended in order to meet this requirement. The
resultant operating frequency can range from 170kHz to
270kHz.
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide
a stable input to the voltage controlled oscillator. The
filter components CLP and RLP determine how fast the
loop acquires lock. Typically RLP =10k and CLP is 0.01F
to 0.1
F.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC1628-SYNC is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1628-SYNC will begin to
skip cycles. The output voltage will continue to be regu-
lated, but the ripple voltage and current will increase.
The minimum on-time for the LTC1628-SYNC is generally
less than 200ns. However, as the peak sense voltage
decreases the minimum on-time gradually increases up to
about 300ns. This is of particular concern in forced
continuous applications with low ripple current at light
loads. If the duty cycle drops below the minimum on-time
limit in this situation, a significant amount of cycle skip-
ping can occur with correspondingly larger current and
voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced on
both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must
be drawn from the inductor primary in order to extract
APPLICATIO S I FOR ATIO
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