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參數(shù)資料
| 型號： | LTC1608CG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 45.5 kSPS ADC Serial Out, Low Power, Compatible to TLC540/545/1540, Single Ch. 8-SOIC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO36 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 1000K |
| 代理商： | LTC1608CG |
13
LTC1608
APPLICATIU
W
U
U
R2
12k
R3
16k
REFERENCE
AMP
22
μ
F
REFCOMP
AGND
V
REF
R1
7.5k
3
4
5
2.500V
4.375V
LTC1608
1608 F12a
BANDGAP
REFERENCE
Figure 12a. LTC1608 Reference Circuit
1
2
3
0.1
μ
F
22
μ
F
ANALOG
INPUT
1608 F12b
LT1019A-2.5
V
OUT
V
IN
5V
A
IN+
A
IN–
V
REF
LTC1608
AGND
REFCOMP
5
4
+
Figure 12b. Using the LT1019-2.5 as an External Reference
A 7.5k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry (see Figure 12b). The reference amplifier gains
the voltage at the V
REF
pin by 1.75 to create the required
internal reference voltage. This provides buffering
between the V
REF
pin and the high speed capacitive DAC.
The reference amplifier compensation pin (REFCOMP, Pin
4) must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 22
μ
F or
greater. Using a 0.1
μ
F ceramic in parallel is recommended.
The V
REF
pin can be driven with a DAC or other means
shown in Figure 13. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1608 reference amplifier will limit
the bandwidth and settling time of this circuit. A settling
time of 20ms should be allowed for after a reference
adjustment.
LTC1608
A
IN+
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
A
IN–
V
REF
REFCOMP
AGND
1608 F13
1
2
3
4
5
22
μ
F
LTC1450
2V TO 2.7V
Figure 13. Driving V
REF
with a DAC
Figure 14a. CMRR vs Input Frequency
INPUT FREQUENCY (Hz)
1k
C
80
70
60
50
40
30
20
10
0
10k
100k
1608 G14a
1M
Differential Inputs
The LTC1608 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of A
IN+
– A
IN–
independent of the
common mode voltage (see Figure 15a). The common
mode rejection holds up to extremely high frequencies
(see Figure 14a). The only requirement is that both inputs
can not exceed the AV
DD
or V
SS
power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or –2.5V.
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