- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10168 > LTC1605-2CG#TR (Linear Technology)IC ADC 16BIT 5V SAMPLING 28SSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LTC1605-2CG#TR |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 18/20闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 16BIT 5V SAMPLING 28SSOP |
| 妯欐簴鍖呰锛� | 2,000 |
| 浣嶆暩(sh霉)锛� | 16 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 100k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 80mW |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 28-SSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊嬪柈绔�锛岄洐妤� |
| 閰嶇敤锛� | DC1255A-A-ND - BOARD SAR ADC LTC1605 |
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7
LTC1605-1/LTC1605-2
APPLICATIONS INFORMATION
WU
U
autozero switch, S3. In this acquire phase, a minimum
delay of 2
swillprovideenoughtimeforthesample-and-
hold capacitor to acquire the analog signal. During the
convert phase, S3 opens, putting the comparator into the
compare mode. The input switch S2 switches CSAMPLE to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the VIN input charge. The SAR contents (a 16-
bit data word) that represents the VIN are loaded into the
16-bit output latches.
Driving the Analog Inputs
The nominal input range for the LTC1605-1 is 0V to 4V or
(1.6VREF) and for the LTC1605-2 the input range is 卤4V
or (
卤1.6VREF). The inputs are overvoltage protected to
卤25V. The input impedance is typically 10k; therefore,
it should be driven by a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If
an amplifier is to be used to drive the input, care should
be taken to select an amplifier with adequate accuracy,
linearity and noise for the application. The following list
is a summary of the op amps that are suitable for driving
the LTC1605-1/LTC1605-2. More detailed information is
available in the Linear Technology data books and
LinearView
TM CD-ROM.
Conversion Details
The LTC1605-1/LTC1605-2 use a successive approxi-
mation algorithm and an internal sample-and-hold cir-
cuit to convert an analog signal to a 16-bit or two byte
parallel output. The ADC is complete with a precision
reference and an internal clock. The control logic pro-
vides easy interface to microprocessors and DSPs. (Please
refer to the Digital Interface section for the data format.)
Conversion start is controlled by the CS and R/C inputs.
At the start of conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider
and S1 to the sample-and-hold capacitor during the
acquire phase and the comparator offset is nulled by the
Figure 1. LTC1605-1/LTC1605-2 Simplified Equivalent Circuit
VDAC
1605-1/2 F01
+
鈥�
CDAC
DAC
S1
SAMPLE
S2
HOLD
CSAMPLE
S
A
R
16-BIT
LATCH
COMPARATOR
SAMPLE
S3
RIN2
RIN1
VIN
LinearView is a trademark of Linear Technology Corporation
1k
50pF
DBN
1k
5V
1605-1/2 TC02
A. VOH TO HI-Z
B. VOL TO HI-Z
Load Circuit for Access Timing
Load Circuit for Output Float Delay
1k
CL
DBN
1k
5V
1605-1/2 TC01
A. HI-Z TO VOH AND VOL TO VOH
B. HI-Z TO VOL AND VOH TO VOL
TEST CIRCUITS
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| IDT72V265LA10PFG | IC FIFO SS 16384X18 10NS 64-TQFP |
| VI-26H-IW-S | CONVERTER MOD DC/DC 52V 100W |
| VI-B73-MY | CONVERTER MOD DC/DC 24V 50W |
| IDT7208L20J | IC FIFO 64KX9 20NS 32PLCC |
| VI-B72-MY | CONVERTER MOD DC/DC 15V 50W |
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鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LTC1605-2CN | 鍔熻兘鎻忚堪:IC ADC 16BIT 5V SAMPLING 28DIP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤碉紱1 鍊嬪柈绔�锛岄洐妤� |
| LTC1605-2CN#PBF | 鍔熻兘鎻忚堪:IC A/D CONV 16BIT SAMPLNG 28-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤�锛�1 鍊嬪柈绔�锛岄洐妤� |
| LTC1605-2IG | 鍔熻兘鎻忚堪:IC A/D CONV 16BIT SAMPLNG 28SSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤碉紱1 鍊嬪柈绔�锛岄洐妤� |
| LTC1605-2IG#PBF | 鍔熻兘鎻忚堪:IC A/D CONV 16BIT SAMPLNG 28SSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤�锛�1 鍊嬪柈绔�锛岄洐妤� |
| LTC1605-2IG#TR | 鍔熻兘鎻忚堪:IC ADC 16BIT 5V SAMPLING 28SSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤�锛�1 鍊嬪柈绔�锛岄洐妤� |
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