參數(shù)資料
型號: LTC1604AIG#TR
廠商: Linear Technology
文件頁數(shù): 3/20頁
文件大?。?/td> 0K
描述: IC ADC 16BIT SAMPL SHTDWN 36SSOP
標準包裝: 2,000
位數(shù): 16
采樣率(每秒): 333k
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 350mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 36-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
LTC1604
11
1604fa
Figure 8. Mode 2. Slow Memory Mode Timing
Figure 9. ROM Mode Timing
APPLICATIONS INFORMATION
RD = CONVST
CS = 0
BUSY
1604 F08
tCONV
t6
DATA (N – 1)
D5 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
t11
t8
t10
t7
RD = CONVST
BUSY
CS = 0
1604 F09
tCONV
t6
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
t10
t11
t8
in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared data bus.
In slow memory and ROM modes (Figures 8 and 9) CS
is tied low and CONVST and RD are tied together. The
MPU starts the conversion and reads the output with the
combined CONVST-RD signal. Conversions are started
by the MPU or DSP (no external sample clock is needed).
In slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (=CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (=CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor
can read the new result and initiate another conversion.
DIFFERENTIAL ANALOG INPUTS
Driving the Analog Inputs
The differential analog inputs of the LTC1604 are easy
to drive. The inputs may be driven differentially or as a
single-ended input (i.e., the AIN– input is grounded). The
AIN+ and AIN– inputs are sampled at the same instant.
Any unwanted signal that is common mode to both in-
puts will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
capacitors at the end of conversion. During conversion
the analog inputs draw only a small leakage current. If the
source impedance of the driving circuit is low, then the
LTC1604 inputs can be driven directly. As source imped-
ance increases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
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