參數(shù)資料
型號(hào): LTC1564CG
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A
中文描述: CONTINUOUS TIME FILTER, PIN PROGRAMMABLE, LOWPASS, PDSO16
封裝: 5.30 MM, PLASTIC, SSOP-16
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 227K
代理商: LTC1564CG
7
LTC1564
AGND (Pin 15):
Analog Ground. The AGND pin is at the
midpoint of an internal resistive voltage divider, develop-
ing a potential halfway between the V
+
and V
pins, with
an equivalent series resistance to the pin of nominally 7k.
(In the shutdown state, analog switch FETs interrupt the
voltage-divider resistors and the AGND pin assumes a
high impedance.) AGND also serves as the internal half-
supply reference in the LTC1564, tied to the noninverting
inputs of all internal op amps and establishing the ground
reference voltage for the IN and OUT pins. Because of this,
very “clean” grounding is recommended, including an
PIU
LTC1564
DIGITAL GROUND PLANE
(IF ANY)
ANALOG
GROUND PLANE
1
SINGLE-POINT
SYSTEM GROUND
2
0.1
μ
F
3
4
5
6
7
1564 F01
8
16
15
14
13
12
11
0.1
μ
F
V
+
10
9
V
Figure 1. Dual Supply Ground Plane Connection
LTC1564
DIGITAL GROUND PLANE
(IF ANY)
ANALOG
GROUND PLANE
1
SINGLE-POINT
SYSTEM GROUND
2
3
4
5
6
7
1564 F01
8
16
V
+
/2
REFERENCE
15
14
13
12
11
0.1
μ
F
1
μ
F
V
+
10
9
Figure 2. Single Supply Ground Plane Connection
analog ground plane surrounding the package. For dual
supply operation, this ground plane will be tied to the 0V
point and the AGND pin should connect directly to the
ground plane (Figure 1). For single supply operation, in
contrast, if the system signal ground is at V
, the ground
plane should tie to V
and the AGND pin should be AC-
bypassed to the ground plane by at least a 0.1
μ
F high
quality capacitor (at least 1
μ
F for best AC performance)
(Figure 2). As with all high dynamic range analog circuits,
performance in an application will reflect the quality of the
grounding.
Table 3. Summary of LTC1564 Digital Controls and Modes
EN
RST
CS/HOLD
F3
1
1
1
X
F2
X
F1
X
F0
X
G3
X
G2 G1
X
G0
X
FUNCTION
Shutdown Mode. Filter Disabled. Latch Holds F and G Inputs Present
when Last CS/HOLD = 0
Shutdown Mode. Filter Disabled. Latch Accepts F and G Inputs
Shutdown Mode. Filter Disabled. Latch Contents (F and G) Reset to All Zeros
Mute Mode. Filter Active, Zero Gain, Reduced Noise
Mute Mode. Filter Active, Zero Gain, Reduced Noise. Latch Contents
(F and G) Reset to All Zeros
Normal Filtering Operation. Latch Holds F and G Inputs Present
when Last CS/HOLD = 0
Normal Filtering Operation. Filter Responds Directly to F and G Input
Pins (See Separate Pin Descriptions)
X
1
1
0
0
1
0
1
0
0
X
0
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
Other Than 0000
X
X
X
X
0
1
0
Other Than 0000
X
X
X
X
X = Doesn’t Matter
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