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參數(shù)資料
| 型號： | LTC1556CGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LEVEL TRANSLTOR W/LDO 20SSOP |
| 標準包裝： | 55 |
| 邏輯功能： | 電平移位器 |
| 位數(shù)： | 1 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 18ns |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 管件 |
9
LTC1555/LTC1556
I/O pin on the SIM side. The second method is to use the
DDRV pin to send data to the SIM and use the DATA pin to
receive data from the SIM. When the DDRV pin is not used,
it should either be left floating or tied to DVCC.
Level Translation with DVCC > VCC
It is assumed that most applications for these parts will
use controller supply voltages (DVCC) less than or equal
to VCC. In cases where DVCC is greater than VCC by more
than 0.6V or so, the parts’ operation will be affected in the
following ways: 1) A small DC current (up to 100
A) will
flow from DVCC to VCC through the DATA pull-up resistor,
N-channel pass device and the I/O pull-up resistor
(except when the part is in shutdown at which time DVCC
is disconnected from VCC by turning off the pass device).
If the VCC load current is less than the DVCC current, the
VCC output may be pulled out of regulation until sufficient
load current pulls VCC back into regulation. 2) When the
SIM is sending data back to the controller, a logic high on
the I/O pin will result in the DATA pin being pulled up to
[VCC + 1/3(DVCC – VCC)], not all the way up to DVCC. For
example, if DVCC is 5V and VCC is 3V, the DATA pin will
only swing from
≈0.1V to 3.67V when receiving data
from the SIM side.
Optional LDO Output
The LTC1556 also contains an internal LDO regulator for
providing a low noise boosted supply voltage for low power
external circuitry (e.g., frequency synthesizers, etc.) Tying
the FB pin to the LDO pin provides a regulated 4.3V at the
LDO output (see Figure 4). A 3.3
F (minimum) capacitor is
APPLICATIONS INFORMATION
WU
U
required to ensure output stability. A 10
F low ESR capaci-
tor is recommended, however, to minimize LDO output
noise. The LDO output may also be used as an auxiliary
switch to VCC. If the FB pin is left floating or is tied to GND,
the LDO pin will be internally connected to the VCC output
through the P-channel pass device. The LDO may be dis-
abled at any time by switching the EN pin from DVCC toGND.
The 4.3V LDO output is usable only when VCC is 5V (or
greater). It is not available when VCC = 3V.
Figure 4. Auxiliary LDO Connections (LTC1556 Only)
VREF
61k
VCC = 5V
1
A
LDO
OFF
ON
10
F
TANT
4.3V
1555/56 F04
ILDO
0mA to
10mA
FB 153k
EN
–
+
10kV ESD Protection
All pins that connect to the SIM (CLK, RST, I/O, VCC, GND)
withstand over 10kV of human body model (100pF/1.5k
)
ESD. In order to ensure proper ESD protection, careful
board layout is required. The GND pins should be tied
directly to a GND plane. The VCC capacitor should be
located very close to the VCC pin and tied immediately to
the GND plane.
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