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參數(shù)資料
| 型號(hào)： | LTC1555L-1.8 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | SIM Power Supply and Level Translator(SMI電源和電平轉(zhuǎn)換器) |
| 中文描述： | SIM卡電源和電平轉(zhuǎn)換（學(xué)校管理新措施電源和電平轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 138K |
| 代理商： | LTC1555L-1.8 |
LTC1555L-1.8
6
APPLICATIU
W
U
U
Capacitor Selection
For best performance, it is recommended that low ESR
(<0.5
) capacitors be used for both C
IN
and C
OUT
to reduce
noise and ripple. The C
IN
and C
OUT
capacitors should be
either ceramic or tantalum and should be 1
μ
F or greater
(ceramic capacitors will produce the smallest output ripple).
If the input source impedance is very low (<0.5
), C
IN
may
not be needed. Increasing the size of C
OUT
to 2.2
μ
F or greater
will reduce output voltage ripple—particularly with high V
IN
voltages (4V or greater). A ceramic capacitor is recom-
mended for the flying capacitor C1 with a value of 0.1
μ
F or
0.22
μ
F.
Output Ripple
Normal LTC1555L-1.8 operation produces voltage ripple
on the V
CC
pin. Output voltage ripple is required for the
parts to regulate. Low frequency ripple exists due to the
hysteresis in the sense comparator and propagation de-
lays in the charge pump enable/disable circuits. High
frequency ripple is also present mainly from the ESR
(equivalent series resistance) in the output capacitor.
Typical output ripple (V
IN
< 4V) under maximum load is
75mV peak-to-peak with a low ESR, 2.2
μ
F output capaci-
tor (V
CC
= 5V).
The magnitude of the ripple voltage depends on several
factors. High input voltages increase the output ripple
since more charge is delivered to C
OUT
per charging cycle.
A large C1 flying capacitor (> 0.22
μ
F) also increases ripple
in step-up mode for the same reason. Large output current
load and/or a small output capacitor (< 1
μ
F) results in
higher ripple due to higher output voltage dV/dt. High ESR
capacitors (ESR > 0.5
) on the output pin cause high
frequency voltage spikes on V
OUT
with every clock cycle.
A 2.2
μ
F ceramic capacitor on the V
CC
pin should produce
acceptable levels of output voltage ripple in nearly all
applications.
Level Translators
All SIMs and smart cards contain a clock input, a reset
input, and a bidirectional data input/output. The
LTC1555L-1.8 provides level translators to allow
controllers to communicate with the SIM. (See Figure 1a
and 1b). The CLK and RST inputs to the SIM are level
shifted from the controller supply rails (DV
CC
and GND) to
the SIM supply rails (V
CC
and GND). The data input to the
SIM may be provided two different ways. The first method
is to use the DATA pin as a bidirectional level translator.
This configuration is only allowed if the controller data
output pin is open drain (all SIM I/O pins are open drain).
Internal pull-up resistors are provided for both the DATA
pin and the I/O pin on the SIM side. The second method
is to use the DDRV pin to send data to the SIM and use the
DATA pin to receive data from the SIM. When the DDRV
pin is not used, it should either be left floating or tied to
DV
CC
.
Shutting Down the DV
CC
Supply
To conserve power, the DV
CC
supply may be shut down
while the V
IN
supply is still active. When the DV
CC
supply
is forced below 1.2V, an undervoltage lockout circuit
forces the LTC1555L-1.8 into shutdown mode regardless
of the status of the M0-M2 pins.
10kV ESD Protection
All pins that connect to the SIM (CLK, RST, I/O, V
CC
, GND)
withstand over 10kV of human body model ESD. In order
to ensure proper ESD protection, careful board layout is
required. The GND pin should be tied directly to a GND
plane. The V
CC
capacitor should be located very close to
the V
CC
pin and tied immediately to the GND plane.
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