參數(shù)資料
型號: LTC1555
廠商: Linear Technology Corporation
英文描述: SIM Power Supply and Level Translator(SMI電源和電平轉(zhuǎn)換器)
中文描述: SIM卡電源和電平轉(zhuǎn)換(學(xué)校管理新措施電源和電平轉(zhuǎn)換器)
文件頁數(shù): 8/12頁
文件大?。?/td> 223K
代理商: LTC1555
8
LTC1555/LTC1556
APPLICATIO
S I
FOR
ATIO
U
reduce the ripple. A larger C
OUT
capacitor (22
μ
F or greater)
will reduce both the low and high frequency ripple due to
the lower C
OUT
charging and discharging dV/dt and the
lower ESR typically found with higher value (larger case
size) capacitors. A low ESR ceramic output capacitor will
minimize the high frequency ripple, but will not reduce the
low frequency ripple unless a high capacitance value is
chosen (10
μ
F or greater). A reasonable compromise is to
use a 10
μ
F to 22
μ
F tantalum capacitor in parallel with a 1
μ
F
to 3.3
μ
F ceramic capacitor on V
OUT
to reduce both the low
and high frequency ripple. An RC filter may also be used
to reduce high frequency voltage spikes (see Figure 1).
W
U
U
hundred milliseconds to completely shut down. To ensure
prompt and proper V
CC
shutdown, always force the M0
and M1 pins to a logic low state before shutting down the
DV
CC
supply (see Figure 2). Similarly, bring the DV
CC
supply to a valid level before allowing the M0 and M1 pins
to go high when coming out of shutdown. This can be
achieved with pull-down resistors from M0 and M1 to
GND if necessary. (Note: shutting down the DV
CC
supply
with V
IN
active is not recommended with early date code
material. Consult factory for valid date code starting point
for shutting down the DV
CC
supply.)
Level Translators
All SIMs and smart cards contain a clock input, reset input
and a bidirectional data input/output. The LTC1555/
LTC1556 provide level translators to allow controllers to
communicate with the SIM (see Figures 3a and 3b). The
CLK and RST inputs to the SIM are level shifted from the
controller supply rails (DV
CC
and GND) to the SIM supply
rails (V
CC
and GND). The data input to the SIM may be
provided two different ways. The first method is to use the
DATA pin as a bidirectional level translator. This configu-
ration is only allowed if the controller data output pin is
open drain (all SIM I/O pins are open drain). Internal pull-
up resistors are provided for both the DATA pin and the
Figure 3b. Level Translator Connections for
One-Directional Controller Side DATA Flow
CIN
RIN
DATA
DDRV
DV
CC
CLK
RST
I/O
V
CC
CLK TO SIM
RST TO SIM
DATA FROM SIM
DATA TO SIM
LTC1555/LTC1556
CONTROLLER
SIDE
SIM SIDE
1555/56 F3b
Figure 3a. Level Translator Connections for
Bidirectional Controller DATA Pin
CIN
RIN
DATA
DDRV
DV
CC
CLK
RST
I/O
V
CC
CLK TO SIM
RST TO SIM
DATA TO/FROM SIM
LTC1555/LTC1556
CONTROLLER
SIDE
SIM SIDE
1555/56 F3a
Figure 2. Recommended DV
CC
Shutdown and Start-Up Timing
M0
DV
CC
0V
M1
DV
CC
0V
DV
CC
DV
CC
0V
V
CC
V
CC
0V
1555/56 F02
Shutting Down the DV
CC
Supply
To conserve power, the DV
CC
supply may be shut down
while the V
IN
supply is still active. When the DV
CC
supply
is brought to 0V, weak internal currents will force the
LTC1555/LTC1556 into shutdown mode regardless of the
voltages present on the M0 and M1 pins. However, if the
M0 and M1 pins are floating or left connected to DV
CC
as
the supply is shut down, the parts may take several
Figure 1. V
CC
Output Ripple Reduction Techniques
15
μ
F
TANTALUM
LT1555/56 F01
V
CC
SIM
V
CC
SIM
V
CC
1
μ
F
CERAMIC
10
μ
F
V
CC
10
μ
F
2
LTC1555/
LTC1556
+
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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