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參數(shù)資料
| 型號： | LTC1520CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 50Mbps Precision Quad Line Receiver |
| 中文描述： | LINE RECEIVER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SO-16 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 214K |
| 代理商： | LTC1520CS |
5
LTC1520
SWITCHU
W
W
APPLICATIO
S I
FOR
ATIO
U
Theory of Operation
Unlike typical line receivers whose propagation delay can
vary by as much as 500% from package to package and
show significant temperature drift, the LTC1520 employs
a novel architecture that produces a tightly controlled and
temperature compensated propagation delay. The differ-
ential timing skew is also minimized between rising and
W
U
U
3.3V
≥
18k
≥
18k
A
B
RECEIVER ENABLED, V
DD
= 5V
RECEIVER DISABLED OR V
DD
= 0V
3.3V
≥
18k
A
B
1520 F05
≥
18k
Figure 5. Input Thevenin Equivalent
EQUIVALU U
V
DD
/2
V
DD
/2
V
DD
/2
V
DD
/2
3V
B1, B2 = 2.5V
2V
CH1 OUT
INPUT
A1, A2
CH2 OUT
t
CH-CH
t
CH-CH
1520 F03
Figure 3. Any Channel to Any Channel Skew, Same Package
Figure 4. Package-to-Package Propagation Delay Skew
falling output edges, and the propagation delays of any
two receivers within a package are very tightly matched.
The precision timing features of the LTC1520 reduce
overall system timing constraints by providing a narrow
6ns window during which valid data appears at the re-
ceiver output. This output timing window applies to all
receivers in all packages over all operating temperatures
Figure 2. Receiver Enable and Disable Timing
Test Circuit and Waveforms
1.5V
1.5V
1.5V
C
L
1k
1k
S1
S2
t
ZH
t
ZL
1.5V
t
LZ
0.2V
0.2V
t
HZ
V
DD
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH
0V
3V
ENABLE
5V
V
OL
V
OH
0V
RECEIVER
OUTPUT
OUT 1
OUT 1
1520 F02
SAME INPUT FOR BOTH PACKAGES
INPUT
A1, B1
V
ID
= 500mV
PACKAGE 1
OUT 1
1520 F04
t
PKG-PKG
t
PKG-PKG
PACKAGE 2
OUT 1
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