參數(shù)資料
型號(hào): LTC1487CN8
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 通用總線功能
英文描述: Ultra-Low Power RS485 with Low EMI, Shutdown and High Input Impedance
中文描述: LINE TRANSCEIVER, PDIP8
封裝: 0.300 INCH, PLASTIC, DIP-8
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 224K
代理商: LTC1487CN8
5
LTC1487
DI (Pin 4):
Driver Input. If the driver outputs are enabled
(DE HIGH) then a LOW on DI forces the outputs A LOW and
B HIGH. A HIGH on DI with the driver outputs enabled will
force A HIGH and B LOW.
GND (Pin 5):
Ground.
A (Pin 6):
Driver Output/Receiver Input.
B (Pin 7):
Driver Output/Receiver Input.
V
CC
(Pin 8):
Positive Supply. 4.75V < V
CC
< 5.25V.
PI
FU
CTIO
N
S
U
U
RO (Pin 1):
Receiver Output. If the receiver output is
enabled (RE LOW), and A > B by 200mV, RO will be HIGH.
If A < B by 200mV, then RO will be LOW.
RE (Pin 2):
Receiver Output Enable. A LOW enables the
receiver output, RO. A HIGH input forces the receiver
output into a high impedance state.
DE (Pin 3):
Driver Outputs Enable. A HIGH on DE enables
the driver output. A and B and the chip will function as a line
driver. A LOW input will force the driver outputs into a high
impedance state and the chip will function as a line
receiver. If RE is HIGH and DE is LOW, the part will enter
a low power (1
μ
A) shutdown state.
Figure 3. Driver/Receiver Timing Test Circuit
Figure 4. Driver Timing Test Load
OUTPUT
UNDER TEST
C
L
S1
S2
V
CC
500
LTC1487 F04
3V
DE
A
B
DI
R
DIFF
C
L1
C
L2
RO
15pF
A
B
RE
LTC1487 F03
Figure 1. Driver DC Test Load
Figure 2. Receiver Timing Test Load
V
OD
A
B
R
R
V
OC
LTC1487 F01
RECEIVER
OUTPUT
C
RL
1k
S1
S2
TEST POINT
V
CC
1k
LTC1487 F02
TEST CIRCUITS
LTC1487 Transmitting
INPUTS
DE
1
1
0
0
OUTPUTS
B
0
1
Z
Z*
RE
X
X
0
1
DI
1
0
X
X
A
1
0
Z
Z*
*Shutdown mode
LTC1487 Receiving
INPUTS
DE
0
0
0
0
OUTPUTS
RO
1
0
1
Z*
RE
0
0
0
1
A – B
0.2V
–0.2V
Inputs Open
X
*Shutdown mode
FU
U
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