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參數(shù)資料
| 型號： | LTC1452IS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 12BIT R-R 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 14µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 680µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
8
LTC1451
LTC1452/LTC1453
sn145123 145123fas
Reference
The LTC1451 includes an internal 2.048V reference, mak-
ing 1LSB equal to 1mV (gain of 2). The LTC1453 has an
internal reference of 1.22V with a full scale of 2.5V (gain of
2.05). The internal reference output is turned off when the
pin is forced above the reference voltage, allowing an
external reference to be connected to the reference pin.
The LTC1452 has no internal reference and the REF pin
must be driven externally. The buffer gain is 2, so the
external reference must be less than VCC/2 and be capable
of driving the 8k minimum DAC resistor ladder.
Voltage Output
The LTC1451 family’s rail-to-rail buffered output can
source or sink 5mA over the entire operating temperature
range while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40
when driving a load to
the rails. The output can drive 1000pF without going into
oscillation.
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The CLK is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse.
The buffered output of the 12-bit shift register is available
on the DOUT pin which swings from GND to VCC.
Multiple LTC1451/LTC1452/LTC1453s may be daisy-
chained together by connecting the DOUT pin to the DIN
pin of the next chip, while the CLK and CS/LD signals
remain common to all chips in the daisy chain. The serial
data is clocked to all of the chips, then the CS/LD signal is
pulled high to update all of them simultaneously.
OPERATIO
U
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