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參數資料
| 型號： | LTC1446LIS8#TR |
| 廠商： | Linear Technology |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL R-R MPWR 8SOIC |
| 標準包裝： | 2,500 |
| 設置時間： | 14µs |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
7
LTC1446/LTC1446L
Resolution (n)
Resolution is defined as the number of digital input bits,
n. It defines the number of DAC output states (2n) that
divide the full-scale range. The resolution does not imply
linearity.
Full-Scale Voltage (VFS)
This is the output of the DAC when all bits are set to one.
Voltage Offset Error (VOS)
The theoretical voltage at the output when the DAC is
loaded with all zeros. The output amplifier can have a true
negative offset, but because the part is operated from a
single supply, the output cannot go below zero. If the
offset is negative, the output will remain near 0V resulting
in the transfer curve shown in Figure 1.
Nominal LSBs:
LTC1446
LSB = 4.095V/4095 = 1mV
LTC1446L LSB = 2.5V/4095 = 0.610mV
Zero Scale Error (ZSE)
The output voltage when the DAC is loaded with all zeros.
Since this is a single supply part this value cannot be less
than 0V.
Integral Nonlinearity (INL)
End-point INL is the maximum deviation from a straight
line passing through the end points of the DAC transfer
curve. Because the part operates from a single supply and
the output cannot go below 0, the linearity is measured
between full scale and the code corresponding to the
maximum offset specification. The INL error at a given
input code is calculated as follows :
INL = [VOUT – VOS – (VFS – VOS)(Code/4095)]/LSB
VOUT= the output voltage of the DAC measured at the given
input code
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and
the ideal 1LSB change between any two adjacent codes.
The DNL error between any two codes is calculated as
follows:
DNL = (
VOUT – LSB)/LSB
VOUT = The measured voltage difference between two
adjacent codes
Figure 1. Effect of Negative Offset
DAC CODE
1446/46L F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
DEFI ITIO S
U
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
Least Significant Bit (LSB)
One LSB is the ideal voltage difference between two
successive codes.
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/4095
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