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參數(shù)資料
| 型號： | LTC1429CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Clock-Synchronized Switched Capacitor Regulated Voltage Inverter |
| 中文描述： | SWITCHED CAPACITOR REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | 0.150 INCH, PLASTIC, SO-14 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 275K |
| 代理商： | LTC1429CS |
5
LTC1429
PI
FU
CTIO
N
S
U
U
effect on output ripple; see the Applications Information
section for more details.
REG (Pin 12/Pin 7):
This is an open drain output that pulls
low when the output voltage is within 5% of the set value.
It will sink 10mA to ground with a 5V supply. The external
circuitry must provide a pull-up or REG will not swing high.
The voltage at REG may exceed V
CC
; it can be pulled up to
12V above ground without damage.
SYNC/SD (Pin 13/Pin 8):
Synchronous Clock Input. A
minimum input clock frequency (60kHz with V
CC
≤
5V and
100kHz with V
CC
= 6.5V) must be applied to this input to
keep the LTC1429 operating normally. An input clock
below the minimum frequency may cause the charge
pump to operate erratically or the device to shut down. A
logic high or low at the SYNC/SD pin will put the device
into SHUTDOWN and drop the supply current to 0.2
μ
A.
The LTC1429 will operate with input square wave of 40%
to 60% duty cycle. For best performance, use a square
wave of 50% duty cycle.
V
CC
(Pin 14/Pin 1):
Power Supply. This requires an input
voltage between 3V and 6.5V. Certain combinations of
output voltage and operating mode may place additional
restrictions on the input voltage; see the Applications
Information section for details. V
CC
must be bypassed to
ground with at least a 0.1
μ
F capacitor, placed in close
proximity to the chip; again, see the Applications Informa-
tion section.
TEST CIR
Figure 2. Tripler Mode
Figure 1. Doubler Mode
1
2
3
4
8
7
6
5
0.1
μ
F
10
μ
F
0.001
μ
F
V
OUT
= –4V
±
5%
5V
3.3
μ
F
V
CC
GND
C1
+
C1
–
SYNC/SD
COMP
REG
OUT
LTC1429-4CS8
+
LTC1429 TC01
F
SYNC
= 700kHz
APPLICATIO
S I
FOR
ATIO
U
MODES OF OPERATION
The LTC1429 uses a charge pump to generate a negative
output voltage that can be regulated to a value either
higher or lower than the original input voltage. It has two
modes of operation: a doubler inverting mode, which can
provide a negative output equal to or less than the positive
power supply, and a tripler inverting mode, which can
provide negative output voltages either larger or smaller in
magnitude than the original positive supply. The tripler
W
U
U
offers greater versatility and wider input range but re-
quires four external capacitors and a 14-pin package; the
doubler offers the SO-8 package and requires only three
external capacitors. The optional compensation capacitor
at ADJ/COMP is used to reduce the ripple output voltage.
Doubler Mode
This mode allows the LTC1429 to generate negative
output voltage magnitudes up to that of the supply voltage,
10
9
8
13
7
11
0.001
μ
F
V
OUT
= –4V
±
5%
3.3
μ
F
LTC1429 TC02
F
SYNC
= 700kHz
NC
NC
10
μ
F
+
V
IN
= 3.3V
V
CC
GND
ADJ
SYNC/SD
R0
OUT
R
ADJ
R1
LTC1429CS
14
6
+
2
3
4
5
C1
+
C1
–
C2
+
C2
–
0.1
μ
F
0.1
μ
F
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