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參數(shù)資料
| 型號： | LTC1427CS8-50#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 0K |
| 描述： | IC D/A CONV 10BIT W/SMBUS 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 550µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1352 (CN2011-ZH PDF) |
5
LTC1427-50
PIN FUNCTIONS
UU
U
SHDN (Pin 1): Shutdown. A logic low puts the chip into
shutdown mode. In shutdown, the digital settings for the
DAC are retained. On release from shutdown, the previ-
ously programmed value for IOUT is reinstated.
AD1, AD0 (Pins 2, 3): Address Selection Pins. Tie these
two pins to either VCC or GND to select one of four SMBus
addresses to which the LTC1427-50 will respond.
GND (Pin 4): Ground. Ground should be tied directly to a
ground plane.
SDA (Pin 5): SMBus Bidirectional Data Input/Digital Out-
put. This pin is an open-drain output and requires a pull-
up resistor or current source to VCC. Data is shifted into the
SDA pin and acknowledged by the SDA pin.
SCL (Pin 6): SMBus Clock Input. Data is shifted into the
SDA pin at the rising edges of the SCL clock during data
transfer.
IOUT (Pin 7): DAC Current Output.
VCC (Pin 8): Voltage Supply. This supply must be kept free
from noise and ripple by bypassing directly to the ground
plane.
SMBUS
INTERFACE
3-BIT
LATCH
REGISTER A
SCL
SDA
AD0
AD1
EN1
10-BIT
LATCH
10-BIT
CURRENT
DAC
1-BIT LATCH
VOLTAGE
REFERENCE
REGISTER C
REGISTER B
31
2
10
8
EN2
POWER-ON
RESET
SHDN
SD
1427 BD
RADJ
IOUT
SD
BLOCK DIAGRAM
W
FU CTIO TABLES
U
AD1
AD0
SMBus Address Location
DAC Power-Up Value
Application
L
0101101
Zero-Scale
CCFL Backlight Control
L
H
0101111
Zero-Scale
General Purpose
H
L
0101110
Zero-Scale
General Purpose
H
0101100
Midscale
LCD Contrast Control
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