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參數(shù)資料
| 型號(hào)： | LTC1426 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 14-bit, 5V, 200KSPS, 4-Channel Unipolar ADC 20-TSSOP -40 to 85 |
| 中文描述： | 微功率雙路6位PWM DAC的 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 222K |
| 代理商： | LTC1426 |
7
LTC1426
TYPICAL APPLICATIO
S
N
microprocessor has “quasi-bidirectional” ports that elimi-
nate additional pull-up resistors to V
CC
. However, external
pull-up resistors should be used if the microprocessor
doesn’t pull the port pins high during reset.
In pulse mode, each clock pulse applied to the CLK1 or
CLK2 input increments the respective counter by one
count. When the counter increases beyond full scale
(111111B), the counter rolls over and becomes zero scale
(000000B). In this way, a single pulse applied to the CLK1
or CLK2 input increases the respective counter by one
count, and 63 pulses decrease that counter by one count.
U
Pushbutton Mode
Figure 5 shows how to use the LTC1426 in a typical
pushbutton application. In pushbutton mode, a logic 1
pulse applied to the CLK1 or CLK2 input increments the
respective counter by one count, and stops incrementing
when the counter reaches full scale (111111B). A logic 0
pulse applied to the CLK1 or CLK2 input decrements the
respective counter by one count, and stops decrementing
when the counter reaches zero scale (000000B). An on-
chip debouncing circuit has a debounce time of 12.8ms to
prevent unintended counts with bouncing pushbuttons.
After a time delay of 410ms, the counter will begin to
increment/decrement at a repeat rate of 19.5Hz if the
pushbutton remains pressed.
Care should be taken to avoid running the CLK and PWM
traces close to one another. Since the CLK pins are high
impedance input nodes in pushbutton mode, current
spikes caused by the switching of the PWM outputs
feedthrough via any stray capacitance between PWM and
CLK lines if not properly routed. Use of proper grounding
techniques and spacing of these lines are highly recom-
mended for optimal performance.
Figure 6 shows a dual digitally programmable current
source using the LT
1013 dual precision op amp and two
NPN transistors (2N3904). After the lowpass filter combi-
nation of R1, C1 (R2, C2), its output swings from 0V to
4.93V. In the configuration shown, this voltage will be
forced across the resistor R
A1
(R
A2
). If R
A1
(R
A2
) is chosen
to be 493
, the output current will range from 0mA at zero
scale to 10mA at full scale. The minimum voltage for V
S
is
determined by the load resistor R
L1
(R
L2
) and Q1(Q2)’s
V
CESAT
voltage. With a load resistor of 50
, the voltage
source can be as low as 5V.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 6. Dual Digitally Programmable Current Source
1
2
3
4
8
7
6
5
CLK1
CLK2
GND
PWM1
SHDN
V
CC
V
REF
PWM2
LTC1426
PWM1
1426 F05
PWM2
PWM1/PWM2: 0V TO 0.985(V
REF
)
LIMITING RESISTOR R PREVENTS SHORTING OF V
AND GND WHEN BOTH
BUTTONS ARE SIMULTANEOUSLY PUSHED. THIS RESISTOR CAN BE PLACED
EITHER IN THE V
OR GND LEG AND THIS DETERMINES THE FUNCTION WHEN
BOTH BUTTONS ARE PUSHED. VALUE OF R < 50k
0.1
μ
F
V
0V TO 5.5V
V
2.7V TO 5.5V
V
CC
2.7V TO 5.5V
SHDN
DOWN
DOWN
UP
UP
R
R
Figure 5. Pushbutton Mode Interface
1
2
3
4
8
7
6
5
CLK1
CLK2
GND
PWM1
SHDN
V
CC
V
REF
PWM2
P1.0
P1.1
LTC1426
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V
–
V
+
OUT B
–IN B
+IN B
LT1013
MPU
(e.g. 8051)
0.1
μ
F
0.1
μ
F
R
A1
493
R1
10k
5V
10V
V
S
V
S
C1
0.1
μ
F
SHDN
2N3904
2N3904
R2
10k
C2
0.1
μ
F
1426 F06
R
L1
I
OUT1
/I
OUT2
: 0mA TO 10mA
R
L1
/R
V
S
: 5V TO 30V
R
L2
R
A2
493
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