fSAMPLE(MAX)
參數(shù)資料
型號： LTC1418ACG
廠商： Linear Technology
文件頁數(shù)： 23/28頁
文件大?。?/td> 0K
描述： IC A/D CONV 14BIT SRL&PAR 28SSOP
標準包裝： 47
位數(shù)： 14
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.5mW 單極；31.5mW 雙極
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類型： 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極
配用： DC178A-ND - BOARD SAR ADC LTC1418
4
LTC1418
TI I G CHARACTERISTICS
W U
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
200
kHz
tCONV
Conversion Time
q
3.4
4
s
tACQ
Acquisition Time
q
0.3
1
s
tACQ + tCONV
Acquisition Plus Conversion Time
q
3.7
5
s
t1
CS to RD Setup Time
(Notes 9, 10)
q
0ns
t2
CS
↓ to CONVST↓ Setup Time
(Notes 9, 10)
q
40
ns
t3
CS
↓ to SHDN↓ Setup Time to Ensure Nap Mode
(Notes 9, 10)
q
40
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time from Nap Mode
(Note 10)
500
ns
t5
CONVST Low Time
(Notes 10, 11)
q
40
ns
t6
CONVST to BUSY Delay
CL = 25pF
q
35
70
ns
t7
Data Ready Before BUSY
↑
20
35
ns
q
15
ns
t8
Delay Between Conversions
(Note 10)
q
500
ns
t9
Wait Time RD
↓ After BUSY↑
q
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
15
30
ns
q
40
ns
CL = 100pF
20
40
ns
q
55
ns
t11
Bus Relinquish Time
820
ns
Commercial
q
25
ns
Industrial
q
30
ns
t12
RD Low Time
q
t10
ns
t13
CONVST High Time
40
ns
t14
Delay Time, SCLK
↓ to DOUT Valid
CL = 25pF (Note 9)
q
35
70
ns
t15
Time from Previous Data Remain Valid After SCLK
↓
CL = 25pF (Note 9)
q
15
25
ns
fSCLK
Shift Clock Frequency
(Notes 9, 10)
0
12.5
MHz
fEXTCLKIN
External Conversion Clock Frequency
(Notes 9, 10)
0.03
4.5
MHz
tdEXTCLKIN
Delay Time, CONVST
↓ to External Conversion Clock Input
(Notes 9, 10)
533
s
tH SCLK
SCLK High Time
(Notes 9, 10)
10
ns
tL SCLK
SCLK Low Time
(Notes 9, 10)
20
ns
tH EXTCLKIN
EXTCLKIN High Time
(Notes 9, 10)
250
ns
tL EXTCLKIN
EXTCLKIN Low Time
(Notes 9, 10)
250
ns
The q denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VCC without latchup.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = 0V or – 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input with AIN
– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1
s after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
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