參數(shù)資料
型號: LTC1412I
廠商: Linear Technology Corporation
英文描述: 12-Bit, 3Msps, Sampling A/D Converter
中文描述: 12位,3Msps,采樣A / D轉(zhuǎn)換器
文件頁數(shù): 6/16頁
文件大小: 499K
代理商: LTC1412I
6
LTC1412
TYPICAL PERFOR U
RIPPLE FREQUENCY (Hz)
–80
A
–40
0
–100
–60
–20
10k
100k
1M
10M
1412 G08
–120
1k
V
SS
V
DD
DGND
Power Supply Feedthrough
vs Ripple Frequency
INPUT FREQUENCY (Hz)
20
C
40
50
70
80
1k
100k
1M
10M
1412 G09
0
10k
60
30
10
Input Common Mode Rejection
vs Input Frequency
PI
FU
CTIO
N
S
U
U
A
IN+
(Pin 1):
Positive Analog Input.
±
2.5V input range
when A
IN–
is grounded.
±
2.5V differential if A
IN–
is
driven.
A
IN–
(Pin 2):
Negative Analog Input. Can be grounded or
driven differentially with A
IN+
.
V
REF
(Pin 3):
2.5V Reference Output.
REFCOMP (Pin 4):
4.06V Reference Bypass Pin.
Bypass to AGND with 10
μ
F ceramic (or 10
μ
F tantalum in
parallel with 0.1
μ
F ceramic).
AGND (Pin 5):
Analog Ground.
D11 to D4 (Pins 6 to 13):
Three-State Data Outputs.
DGND (Pin 14):
Digital Ground for Internal Logic.
D3 to D0 (Pins 15 to 18):
Three-State Data Outputs.
OGND (Pin 19):
Digital Ground for the Output Drivers.
OV
DD
(Pin 20):
Positive Supply for the Output Drivers. Tie
to Pin 28 when driving 5V logic. Tie to 3V when driving
3V logic.
DV
DD
(Pin 21):
5V Positive Supply. Tie to Pin 28. Bypass
to AGND with 0.1
μ
F ceramic.
DGND (Pin 22):
Digital Ground for Internal Logic.
CONVST (Pin 23):
Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 24):
Chip Select. This input must be low for the
ADC to recognize the CONVST inputs.
BUSY (Pin 25):
The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
V
SS
(Pin 26):
–5V Negative Supply. Bypass to AGND with
10
μ
F ceramic (or 10
μ
F tantalum in parallel with 0.1
μ
F
ceramic).
DV
DD
(Pin 27):
5V Positive Supply. Tie to Pin 28.
AV
DD
(Pin 28):
5V Positive Supply. Bypass to AGND with
10
μ
F ceramic (or 10
μ
F tantalum in parallel with 0.1
μ
F
ceramic).
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