參數(shù)資料
型號(hào)： LTC1412CG
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 12-Bit, 3Msps, Sampling A/D Converter
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝： 0.209 INCH, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 499K
代理商： LTC1412CG
13
LTC1412
APPLICATIO
S I
N
FOR
ATIO
U
–5V
W
U
plane to the power supply should be low impedance.
Digital circuitry grounds must be connected to the digital
supply common. Low impedance analog and digital power
supply lines are essential to low noise operation of the
ADC. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC1412 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN+
and A
IN–
leads
will be rejected by the input CMRR. The A
IN–
input can be
used as a ground sense for the A
IN+
input; the LTC1412
will hold and convert the difference voltage between A
IN+
and A
IN–
. The leads to A
IN+
(Pin 1) and A
IN–
(Pin 2) should
be kept as short as possible. In applications where this is
not possible, the A
IN+
and A
IN–
traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10
μ
F bypass
capacitors should be used at the V
DD
and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10
μ
F tantalum capacitors
in parallel with 0.1
μ
F ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
Figure 12. Power Supply Grounding Practice
LTC1412
A
IN+
ANALOG INPUT
A
IN–
V
REF
REFCOMP
AGND
1412 F11b
1
2
3
R4
100
R2
50k
R3
24k
R6
24k
R1
50k
R5
47k
4
5
10
μ
F
Figure 11b. Offset and Full-Scale Adjust Circuit
–0.61mV (i.e., –0.5LSB) at A
IN+
and adjust the offset at
the A
IN–
input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to A
IN+
and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1412, a
printed circuit board with ground plane is required. Layout
for the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital line
alongside an analog signal line.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pins 22 and 14 (DGND) and Pin 19 (OGND)
and all other analog grounds should be connected to this
single analog ground point. The REFCOMP bypass capaci-
tor and the DV
DD
bypass capacitor should also be con-
nected to this analog ground plane, see Figure 12. All
analog circuitry grounds should be terminated to this
analog ground plane. The ground return from the ground
1412 F12
A
IN
+
AGND
REFCOMP
V
SS
AV
DD
LTC1412
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
5
4
2
26
OV
DD
DV
DD
20
21, 27
28
OGND
DGND
14, 22
19
POWER
SUPPLY
GROUND
1
0.1
μ
F
A
IN
–
0.1
μ
F
0.1
μ
F
10
μ
F
ANALOG GROUND PLANE
+
+
10
μ
F
10
μ
F
+
+
相關(guān)PDF資料
PDF描述
LTC1412I 12-Bit, 3Msps, Sampling A/D Converter
LTC1412IG 12-Bit, 3Msps, Sampling A/D Converter
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LTC1414CGN Dual, Low Voltage, LinCMOS(TM) Differential Comparator 8-SOIC 0 to 70
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參數(shù)描述
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