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參數資料
| 型號： | LTC1409 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 12-Bit, 800ksps Sampling A/D Converter with Shutdown(12位, 800ksps,采樣模數轉換器(帶關斷)) |
| 中文描述： | 12位，800ksps與關機采樣A / D轉換器（12位，800ksps，采樣模數轉換器（帶關斷）） |
| 文件頁數： | 10/20頁 |
| 文件大?。?/td> | 343K |
| 代理商： | LTC1409 |
10
LTC1409
APPLICATIO
S I
FOR
ATIO
U
0
W
U
U
FREQUENCY (Hz)
0
A
–20
–40
–60
–80
–100
–120
100k
200k
300k
400k
LTC1409 F05
50k
150k
250k
350k
fb – fa
2fb – fa
2fa – fb
2fa
2fb
3fb
fa + 2fb
3fa
2fa
+ fb
fa + fb
f
SAMPLE
= 800kHz
f
IN1
f
IN2
= 111.9995117kHz
Figure 5. Intermodulation Distortion Plot
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1409 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1409 are easy to
drive. The inputs may be driven differentially or as a
single-ended input (i.e., the –A
IN
input is grounded). The
+A
IN
and –A
IN
inputs are sampled at the same instant.
Any unwanted signal that is common mode to both
inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
capacitors at the end of conversion. During conversion
the analog inputs draw only a small leakage current. If the
source impedance of the driving circuit is low then the
LTC1409 inputs can be driven directly. As source imped-
ance increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance,
a buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next conver-
sion starts (settling time must be 150ns for full through-
put rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (<100
) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of 1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100
. The second requirement is that the closed-loop
SOURCE RESISTANCE (k
)
0.01
A
μ
s
1
LTC1409 F06
0.1
0.01
0.1
1
10
100
10
Figure 6. Acquisition Time vs Source Resistance
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