參數(shù)資料
型號(hào)： LTC1405
廠商： Linear Technology Corporation
英文描述： 12-Bit, 5Msps, Sampling ADC(12位, 5Msps,采樣模數(shù)轉(zhuǎn)換器)
中文描述： 12位，5Msps，采樣ADC（12位，5Msps，采樣模數(shù)轉(zhuǎn)換器）
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 339K
代理商： LTC1405
4
LTC1405
DIGITAL U
D OUTPUTS
temperature range, otherwise specifications are at T
A
= 25
°
C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)
U
The
G
denotes the specifications which apply over the full operating
SYMBOL
I
IN
C
IN
V
OH
PARAMETER
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
CONDITIONS
V
IN
= 0V to V
DD
MIN
TYP
MAX
±
10
UNITS
POWER REQUIRW
range, otherwise specifications are at T
A
= 25
°
C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)
U
The
G
denotes the specifications which apply over the full operating temperature
SYMBOL
V
DD
V
SS
PARAMETER
Positive Supply Voltage
Negative Supply Voltage
CONDITIONS
(Note 10)
Dual Supply Mode
Single Supply Mode
MIN
4.75
–5.25
TYP
MAX
5.25
–4.75
UNITS
V
V
V
0
I
DD
I
SS
P
D
Positive Supply Current
Negative Supply Current
Power Dissipation
G
23
0.8
115
28
1.2
145
mA
mA
mW
G
G
TW U
range, otherwise specifications are at T
A
= 25
°
C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)
The
G
denotes the specifications which apply over the full operating temperature
SYMBOL
f
SAMPLE
t
CONV
t
ACQ
t
H
t
L
t
AD
PARAMETER
Sampling Frequency
Conversion Time
Acquisition Time
CLK High Time
CLK Low Time
Aperture Delay of Sample-and-Hold
CONDITIONS
MIN
0.02
TYP
MAX
5
180
UNITS
MHz
G
G
150
50
100
100
–250
ns
ns
ns
ns
ps
G
20
20
20
(Note 9)
(Note 9)
G
G
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below V
SS
they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. GAIN is not clamped to V
DD
. When CLK
is taken above V
DD
, it will be clamped by an internal diode. The CLK pin
can handle input currents of greater than 100mA above V
DD
without
latchup.
Note 5:
V
DD
= 5V, V
SS
= –5V or 0V, f
SAMPLE
= 5MHz, t
r
= t
f
= 5ns unless
otherwise specified.
G
μ
A
pF
V
V
V
V
V
V
V
V
mA
mA
1.8
4.74
4.71
2.6
0V
DD
= 4.75V, I
O
= –10
μ
A
0V
DD
= 4.75V, I
O
= –200
μ
A
0V
DD
= 2.7V, I
O
= –10
μ
A
0V
DD
= 2.7V, I
O
= –200
μ
A
0V
DD
= 4.75V, I
O
= 160
μ
A
0V
DD
= 4.75V, I
O
= 1.6mA
0V
DD
= 2.7V, I
O
= 160
μ
A
0V
DD
= 2.7V, I
O
= 1.6mA
V
OUT
= 0V
V
OUT
= V
DD
G
4.0
G
2.3
V
OL
Low Level Output Voltage
0.05
0.10
0.05
0.10
50
35
G
0.4
G
0.4
I
SOURCE
I
SINK
Output Source Current
Output Sink Current
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