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參數(shù)資料
| 型號： | LTC1402IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2.2MSPS SHDN 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2.2M |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
15
LTC1402
APPLICATIONS INFORMATION
WU
U
0000 0000 0000 and 0000 0000 0001. For full-scale ad-
justment in Figures 10a and 10b, apply an input voltage of
2.0465V (FS – 1.5LSBs) to AIN+ and adjust R5 until the
output code flickers between 1111 1111 1110 and 1111
1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1402, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all
other analog grounds should be connected directly to an
analog ground plane. Pin 9 (OGND) should be connected
near Pin13 (DGND), where the analog ground plane ties to
the logic system ground. The VREF bypass capacitor and
the DVDD bypass capacitor should also be connected to
this analog ground plane, see Figure 11. No other digital
grounds should be connected to this analog ground plane.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as
possible. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
as possible.
The LTC1402 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1402 will
hold and convert the difference voltage between AIN+ and
AIN– . The leads to AIN+ (Pin 3) and AIN– (Pin 4) should be
kept as short as possible. In applications where this is not
possible, the AIN+ and AIN– traces should be run side-by-
side to cancel noise coupling.
SUPPLY BYPASSING
High quality, low series resistance 10
F ceramic bypass
capacitors should be used at the VDD and VREF pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively, 10
F tantalum capaci-
tors in parallel with 0.1
F ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
POWER-DOWN MODES
Upon power-up, the LTC1402 is initialized to the active
state and is ready for conversion. The Nap and Sleep Mode
waveforms show the power-down modes for the LTC1402.
The SCK and CONV inputs control the power-down modes
(see Timing Diagrams). Two rising edges at CONV, with-
out any intervening rising edges at SCK, put the LTC1402
in Nap mode and the power drain drops from 90mW to
Figure 11. Power Supply Grounding Practice
1402 F11
AIN
+
AGND2
AGND1
VREF
AVDD DVDD
OVDD
DOUT
OGND
LTC1402
DIGITAL
SYSTEM
GROUND
10
F
10
F
ANALOG
INPUT
CIRCUITRY
614
5
4
112
13
9
10
12
3V TO 5V
DGND
3
AIN
–
VSS
2
ANALOG GROUND PLANE
10
F
+
–
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