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參數(shù)資料
| 型號(hào)： | LTC1401IS8 |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT W/SHTDN 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
4
LTC1401
1401fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
200
kHz
tCONV
Conversion Time
fCLK = 3.2MHz
●
4.1
s
tACQ
Acquisition Time
315
ns
fCLK
CLK Frequency
●
0.1
3.2
MHz
tCLK
CLK Pulse Width
(Notes 5 and 8)
●
60
ns
tWK(NAP)
Time to Wake Up from Nap Mode
350
ns
t1
CLK Pulse Width to Return to Active Mode
●
60
ns
t2
CONV
↑ to CLK↑Setup Time
●
100
ns
t3
CONV
↑After Leading CLK↑
●
0ns
t4
CONV Pulse Width
(Note 7)
●
50
ns
t5
Time from CLK
↑to Sample Mode
80
ns
t6
Aperture Delay of Sample-and-Hold
Jitter < 50ps
45
ns
t7
Minimum Delay Between Conversion
(Note 5)
●
350
550
ns
t8
Delay Time, CLK
↑ to DOUT Valid
CLOAD = 20pF
●
60
120
ns
t9
Delay Time, CLK
↑to DOUT Hi-Z
CLOAD = 20pF
●
60
120
ns
t10
Time from Previous Data Remains Valid After CLK
↑
CLOAD = 20pF
●
15
50
ns
t11
Minimum Time Between Nap/Sleep Request to Wake Up Request (Notes 5 and 8)
●
50
ns
TI I G CHARACTERISTICS
W U
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below GND or above VCC, they
will be clamped by internal diodes. This product can handle input currents
greater than 40mA without latch-up if the pin is driven below GND or
above VCC.
Note 4: When these pin voltages are taken below GND, they will be clamped
by internal diodes. This product can handle input currents greater than 40mA
without latch-up if the pin is driven below GND. These pins are not clamped
to VCC.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 120ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
Note 8: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.
The
● denotes specifications which apply over the full operating temperature range,
unless otherwise noted specifications are at TA = 25°C. VCC = 3V, fSAMPLE = 200kHz, tr = tf = 5ns, unless otherwise specified.
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