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參數(shù)資料
| 型號(hào)： | LTC1390CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Hex 2-Input NAND Drivers 20-PDIP 0 to 70 |
| 中文描述： | 8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | LTC1390CS |
5
LTC1390
PI
FU
CTIO
N
S
U
U
S0 to S7 (Pins 1 to 8):
Analog Multiplexer Inputs/Analog
Demultiplexer Outputs.
GND (Pin 9):
Digital Ground. Connect to system ground.
CLK (Pin 10):
System Clock (TTL/CMOS Compatible). The
clock synchronizes the channel selection bits and the
serial data transfer from Data 1 to Data 2.
CS (Pin 11):
Chip Select Input (TTL/CMOS Compatible). A
logic high on this input enables LTC1390 to read in the
channel selection bits and allow data transfer from Data 1
to Data 2. A logic low enables the desired channel for
analog signal transmission and allows data transfer from
Data 2 to Data 1.
Data 1 (Pin 12):
Bidirectional Digital Input/Output (TTL/
CMOS Compatible). Input for the channel selection bits.
Data 2 (Pin 13):
Bidirectional Digital Input/Output (TTL/
CMOS Compatible).
V
–
(Pin 14):
Negative Supply.
D (Pin 15):
Analog Multiplexer Output/Analog
Demultiplexer Input.
V
+
(Pin 16):
Positive Supply.
Figure 2: Multiplexer Operation
ANY
ANALOG
INPUTS
D
DATA 1
EN = HIGH
B2
B1
B0
EN = LOW
B2
B1
B0
LTC1390 F02
CLK
CS
t
ON
t
OFF
APPLICATIU
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1390 required for MUX operation. The
LTC1390 uses Data 1 to select its 8 channels and a chip
select input CS to switch on the selected channel as shown
in Figure 2.
U
W
U
When CS is high, the input data on the Data 1 pin is latched
into the 4-bit shift register on each rising clock edge. The
input data consists of an “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. To ensure correct operation, the CS must be
pulled low before the next rising clock edge.
Once the CS is pulled low, all channels are simultaneously
switched off to ensure a break-before-make interval. After
a delay of t
ON
, the selected channel is switched on allowing
signal transmission. The selected channel remains on
until the next falling edge of CS, and after a delay of t
OFF
,
it terminates the analog signal transmission and subse-
quently allows the selection of the next channel. If “EN” bit
is logic low, as illustrated in the second data sequence, it
disables all channels and there will be no analog signal
4-BIT SHIFT
REGISTER
CLK
DATA 1
CS
CONTROL
LOGIC
MUX
BLOCK
ANALOG
INPUT
ANALOG
OUTPUT
LTC1390 F01
Figure 1: Simplified Block Diagram of the MUX Operation
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