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參數(shù)資料
| 型號(hào)： | LTC1340 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Low Noise, Voltage-Boosted Varactor Driver(低噪聲，升壓型，變抗器驅(qū)動(dòng)器) |
| 中文描述： | 低噪聲，電壓，細(xì)看變?nèi)荻O管驅(qū)動(dòng)器（低噪聲，升壓型，變抗器驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 215K |
| 代理商： | LTC1340 |
7
LTC1340
APPLICATIO
S I
FOR
ATIO
U
Amplifier transconductance is typically 1800
μ
mho. With a
1nF external capacitor at the amplifier output, the band-
width is 125kHz. The amplifier transconductance varies
with temperature and process. The minimum recom-
mended C
OUT
is 220pF with a typical bandwidth of 566kHz.
The slew rate of the amplifier is:
SR = I
OUT
/C
OUT
The amplifier typically sinks or sources 20
μ
A, allowing it
to slew a 1nF output capacitance at 20V/ms, or 5V in
250
μ
s.
The on-chip amplifier feedback network is set for a DC gain
of 2.3 with an input offset of 0.35V as shown in the typical
curves. The amplifier allows a rail-to-rail input swing with
a 3V supply and provides a 5V swing at the output. The
output swings to within millivolts of the AV
CC
voltage and
to about 100mV above AGND. The input stage of the
amplifier is powered from AV
CC
and accepts full GND to
V
CC
rail-to-rail input signals without exceeding the input
common mode range. The output noise of the amplifier is
typically 15
μ
V
RMS
at frequencies between 1kHz and
100kHz.
There are two feedthrough signals at the amplifier OUT pin
from the charge pump, the main component at 4MHz and
the second harmonic signal at 8MHz. The 4MHz
feedthrough is typically below 50
μ
V with C
OUT
equal to 1nF
and C
CP
equal to 0.1
μ
F. The feedthrough signal decreases
in amplitude when larger C
OUT
is used. Most systems
W
U
U
should require no additional filtering. Additional filtering
to reduce feedthrough noise is possible by inserting a
resistor or a ferrite bead between OUT and C
OUT
.
Hookup
The two sections of the LTC1340 are carefully shielded
from each other inside the chip, but care must also be
taken in the external hookup to minimize noise at the
amplifier output. The two halves of the chip should only
meet electrically where the CP and AV
CC
pins connect
together and at the common point of AGND and PGND.
Separate PGND and AGND as much as possible. AGND is
the amplifier ground. Connect it to a ground plane and as
close to the VCO ground as possible. Bypass V
CC
and CP
to PGND with a 0.1
μ
F capacitor. Select high quality, low
ESR and low ESL surface mount ceramic capacitors for
both the CP and the VCC bypass capacitors. Poor grade
capacitors will result in unacceptable ripple amplitude or
ringing characteristics. Connect both terminals of the
bypass capacitors as close to the chip as possible to
minimize charge pump output ripple amplitude and ground
currents in the rest of the system. Keep IN and OUT away
from V
CC
, CP and AV
CC
as much as possible. Crosstalk
from V
CC
, CP and AV
CC
PCB traces to IN and OUT PCB
traces can be minimized by routing AGND PCB traces as
shield as shown in Figures 1 and 2. Connect the 1nF output
capacitor close to the varactor diode and return it to the
AGND plane. The SHDN and IN pins, should not be allowed
to go below PGND potential as the ESD diode forms an
NPN and bleeds the charge pump output.
Figure 1. Suggested Surface Mount PCB Layout for LTC1340CS8
0.1
μ
F
0.1
μ
F
LTC1340CS8
1nF
VARACTOR
DIODE
1340 F01
PIN 1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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