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參數(shù)資料
| 型號： | LTC1329CS8-50#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 8BIT MICROPWR 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 840µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1352 (CN2011-ZH PDF) |
4
LTC1329-10/
LTC1329-50/LTC1329A-50
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
TEMPERATURE (
°C)
0
FULL-SCALE
I
OUT
ERROR
(LSB)
3
2
1
0
–1
–2
–3
30
50
1329 G05
10
20
40
60
70
VCC = 3.3V
V(IOUT) = 0.45V
LTC1329-50
LTC1329-10
CODE
0
INL
(LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
64
128
160
1329 TPC04
32
96
192 224
256
TA = 25°C
VCC = 3.3V
V(IOUT) = 0.45V
LTC1329-10/LTC1329-50 Full-
Scale Current vs Temperature
SUPPLY VOLTAGE (V)
0
FULL-SCALE
I
OUT
ERROR
(LSB)
2
1
0
–1
–2
35
1329 G06
12
46
7
TA = 25°C
V(IOUT) = 0.45V
LTC1329-50
LTC1329-10
LTC1329-10/LTC1329-50
Supply Voltage Rejection
LTC1329-50 INL vs Code
PIN FUNCTIONS
UU
U
IOUT (Pin 1): DAC Current Output. In 3.3V or 5V systems,
the DAC current output can be biased from – 15V to 2V or
– 15V to 2.5V respectively.
VCC (Pin 2): Voltage Supply (2.7V ≤ VCC ≤ 6.5V). This
supply must be kept free from noise and ripple by bypass-
ing directly to the ground plane.
SHDN (Pin 3): Shutdown. A logic low puts the chip
into Shutdown mode. The digital setting for the DAC is
retained.
CLK (Pin 4): Shift Clock. This clock synchronizes the serial
data in 3-wire mode. This pin has a Schmitt trigger input.
CS (Pin 5): Chip Select Input. In 3-wire mode, a logic low
on this CS pin enables the LTC1329. Upon power-up, a
logic high at CS puts the chip into pulse mode. If CS ever
goes low, the chip is configured in 3-wire mode until the
next power is cycled.
GND (Pin 6): Ground. Ground should be tied directly to a
ground plane.
DIN (UP/DN)(Pin 7): Data Input. In 3-wire mode, the DAC
data is shifted into DIN on the rising edge of CLK. In pulse
mode, upon power-up a logic high at DIN puts the counter
into increment-only mode. If DIN ever goes low, the
IOUT BIAS VOLTAGE (V)
–15
FULL-SCALE
I
OUT
ERROR
(LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–6
0
1329 G07
–12
–9
–3
3
6
TA = 25°C
VCC = 3.3V
LTC1329-50
LTC1329-10
LTC1329-10/LTC1329-50
Bias Voltage Rejection
(Full-Scale Current)
IOUT BIAS VOLTAGE (V)
–15
ZERO-SCALE
I
OUT
CURRENT
(nA)
50
40
30
20
10
0
–10
–20
–30
–40
–50
–6
0
1329 G08
–12
–9
–3
3
6
LTC1329-10
LTC1329-50
LTC1329-10/LTC1329-50
Bias Voltage Rejection
(Zero-Scale Current)
SUPPLY VOLTAGE (V)
2.7
MAXIMUM
I
OUT
BIAS
VOLTAGE
(V)
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
3.7
4.7
5.2
1329 TPC09
3.2
4.2
5.7
6.2
6.7
TA = 25°C
IOUT = FULL-SCALE CURRENT
Maximum IOUT Bias Voltage
vs Supply Voltage
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