Figure 11b. Setup Time (tsuCS
參數(shù)資料
型號(hào): LTC1292BCN8
廠商: Linear Technology
文件頁(yè)數(shù): 7/24頁(yè)
文件大?。?/td> 0K
描述: IC DATA ACQ SYSTEM 12BIT 8-DIP
標(biāo)準(zhǔn)包裝: 50
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 60k
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 單電源
電源電壓: 5V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
15
LTC1292/LTC1297
12927fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 11b. Setup Time (tsuCS) Is Met for the LTC1292
Figure 11c. Setup Time (tsuCS) Is Not Met for the LTC1292
tsuCS. With the minimum possible sample time of 6s,
RSOURCE+ < 5k and C1 < 20pF will provide adequate
settling time. In general for both the LTC1292 and LTC1297
keep the product of the total resistance and the total
capacitance less than tSMPL/9. If this condition can not be
met, then make C1 > 0.47
F (see RC Input Filtering
section).
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 11a,
11b, 11c and 12). During the conversion, the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. It is critical that the
DOUT
CLK
B11
HI-Z
B9
B10
LTC1292/7 F11b
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
DOUT
CLK
B11
HI-Z
B10
LTC1292/7 F11c
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
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