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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LTC1291CCN8#PBF |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 7/20闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DATA ACQ SYSTEM 12BIT 8-DIP |
| 妯欐簴鍖呰锛� | 50 |
| 椤炲瀷锛� | 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 12 b |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 闆绘簮闆诲锛� | 5V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-PDIP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1346 (CN2011-ZH PDF) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�鐣跺墠绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�
15
LTC1291
1291fa
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 7. Parasitic Resistance in the VCC and GND Leads
Figure 8. Analog Input Equivalent Circuit
5V
VCC
GND
LTC1291 F07
RP1
RP2
鈥�
+
REF+
REF鈥�
D/A
LTC1291
3RD CLK
鈫�
RON = 500
CIN =
100pF
LTC1291
鈥�+鈥�
INPUT
RSOURCE +
VIN +
C1
鈥溾€撯€�
INPUT
RSOURCE 鈥�
VIN 鈥�
C2
LTC1291 F08
5TH CLK
鈫�
or GND lead will cause gain errors and offset errors (Figure
7). For the best performance the LTC1291 should be
soldered directly to the PC board. If the source can not be
placed next to the pin and the gain parameter is important,
the pin should be Kelvin-sensed to eliminate parasitic
resistances due to long PC traces. For example, 0.1
of
resistance in the VCC lead can typically cause 0.5LSB
(ICC 0.1/VCC) of gain error for VCC = 5V.
When the input MUX is selected for single-ended input the
minus terminal is connected to GND internally on the die.
Any parasitic resistance from the GND pin to the ground
plane will lead to an offset voltage (ICC RP2).
Source Resistance
The analog inputs of the LTC1291 look like a 100pF
capacitor (CIN) in series with a 500 resistor (RON). CIN
gets switched between 鈥�+鈥� and 鈥溾€撯€� inputs once during
each conversion cycle. Large external source resistors
and capacitances will slow the settling of the inputs. It is
important that the overall RC time constant is short
enough to allow the analog inputs to settle completely
within the allowed time.
鈥�+鈥� Input Settling
The input capacitor is switched onto the 鈥�+鈥� input during
the sample phase (tSMPL, see Figure 9). The sample period
is 2.5 CLK cycles before a conversion starts. The voltage
on the 鈥�+鈥� input must settle completely within the sample
period. Minimizing RSOURCE+ and C1 will improve the
settling time. If large 鈥�+鈥� input source resistance must be
used, the sample time can be increased by using a slower
CLK frequency. With the minimum possible sample time
of 2.5
s, RSOURCE+ < 1.0k and C1 < 20pF will provide
adequate settle time.
鈥溾€撯€� Input Settling
At the end of the sample phase the input capacitor switches
to the 鈥溾€撯€� input and the conversion starts (see Figure 9).
During the conversion, the 鈥�+鈥� input voltage is effectively
鈥渉eld鈥� by the sample-and-hold and will not affect the
conversion result. It is critical that the 鈥溾€撯€� input voltage be
free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing RSOURCE鈥� and C2 will
improve settling time. If large 鈥溾€撯€� input source resistance
must be used, the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 1MHz,
RSOURCE鈥� < 250 and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp, it is
important that the op amp settles within the allowed time
(see Figure 9). Again the 鈥�+鈥� and 鈥溾€撯€� input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps including the LT1006 and
LT1013 single supply op amps can be made to settle well
even with the minimum settling windows of 2.5
s (鈥�+鈥�
input) and 1
s (鈥溾€撯€� input) that occurs at the maximum
clock rate of 1MHz. Figures 10 and 11 show examples
adequate and poor op amp settling.
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