- 鎮ㄧ従鍦ㄧ殑浣嶇疆锛�璨疯常IC缍� > PDF鐩寗9517 > LTC1290DCSW#PBF (Linear Technology)IC DATA ACQ SYS 12BIT 20-SOIC PDF璩囨枡涓嬭級
鍙冩暩璩囨枡
| 鍨嬭櫉锛� | LTC1290DCSW#PBF |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩锛� | 11/32闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DATA ACQ SYS 12BIT 20-SOIC |
| 妯欐簴鍖呰锛� | 38 |
| 椤炲瀷锛� | 鏁告摎閲囬泦绯荤当锛圖AS锛�锛孉DC |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 12 b |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 50k |
| 鏁告摎鎺ュ彛锛� | 涓茶锛屽苟鑱� |
| 闆诲闆绘簮锛� | 闆� ± |
| 闆绘簮闆诲锛� | ±5 V锛�5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 20-SOIC |
| 鍖呰锛� | 绠′欢 |
| 鐢㈠搧鐩寗闋侀潰锛� | 1346 (CN2011-ZH PDF) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�鐣跺墠绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�
19
LTC1290
1290fe
V鈥�
22
F
TANTALUM
VCC
LTC1290 F06
0.1
F
CERAMIC
DISK
ANALOG
GROUND
PLANE
1
10
20
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 6. Example Ground Plane for the LTC1290
Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce
errors or noise in the output code. VCC noise and ripple can
be kept below 0.5mV by bypassing the VCC pin directly to
the analog ground plane with a 22
F tantalum capacitor
and leads as short as possible. The lead from the device to
the VCC supply should also be kept to a minimum and the
VCC supply should have a low output impedance such as
that obtained from a voltage regulator (e.g., LT1761).
Figures 7 and 8 show the effects of good and poor VCC
bypassing.
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1290 have
capacitive switching input current spikes. These current
Figure 7. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors
VERTICAL:
0.5mV/DIV
HORIZONTAL: 10
s/DIV
CS
VCC
Figure 8. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
HORIZONTAL: 10
s/DIV
VERTICAL:
0.5mV/DIV
spikes settle quickly and do not cause a problem. How-
ever, if large source resistances are used or if slow settling
op amps drive the inputs, care must be taken to insure that
the transients caused by the current spikes settle com-
pletely before the conversion begins.
Source Resistance
The analog inputs of the LTC1290 look like a 100pF
capacitor (CIN) in series with a 500 resistor (RON) as
shown in Figure 9. CIN gets switched between the selected
鈥�+鈥� and 鈥溾€撯€� inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle within the allowed time.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-B5T-MY-S | CONVERTER MOD DC/DC 6.5V 50W |
| D38999/26JH55JB | CONN PLUG 55POS STRAIGHT W/SCKT |
| VE-B5R-MY-S | CONVERTER MOD DC/DC 7.5V 50W |
| VE-B5P-MY-S | CONVERTER MOD DC/DC 13.8V 50W |
| D38999/26WJ90SN | CONN PLUG 46POS STRAIGHT W/SCKT |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁� |
鍙冩暩鎻忚堪 |
|---|---|
| LTC1290DIN | 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-DIP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁告摎閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 椤炲瀷:鏁告摎閲囬泦绯荤当锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁告摎鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| LTC1290DIN#PBF | 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁告摎閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 椤炲瀷:鏁告摎閲囬泦绯荤当锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁告摎鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| LTC1290DISW | 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁告摎閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 椤炲瀷:鏁告摎閲囬泦绯荤当锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁告摎鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| LTC1290DISW#PBF | 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁告摎閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 椤炲瀷:鏁告摎閲囬泦绯荤当锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁告摎鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| LTC1290DISW#TR | 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 5V 20SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁告摎閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 椤炲瀷:鏁告摎閲囬泦绯荤当锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁告摎鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
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