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參數(shù)資料
| 型號： | LTC1283CN |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 0K |
| 描述： | IC DATA ACQ SYS 10BIT 3V 20-DIP |
| 標準包裝： | 18 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 15k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 雙 ± |
| 電源電壓： | ±3.3V，3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
16
LTC1283
1283fb
6. Sharing the Serial Interface
The LTC1283 can share the same 3-wire serial interface
with other peripheral components or other LTC1283s (see
Figure 5). In this case, the CS signals decide which
LTC1283 is being addressed by the MPU.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
MNEMONIC
DESCRIPTION
MOV P1, #02H
INITIALIZE PORT 1 (BIT 1 IS MADE AN
INPUT)
CLR P1.3
SCLK GOES LOW
SETB P1.4
CS GOES LOW
CONTINUE: MOV A, #0DH
DIN WORD FOR THE LTC1283 IS PLACED
IN ACC
CLR P1.4
CS GOES LOW
MOV R4, #08
LOAD COUNTER
NOP
DELAY FOR DEGLITCHER
LOOP:
MOV C, P1.1
READ DATA BIT INTO CARRY
RLC A
ROTATE DATA BIT INTO ACC
MOV P1.2, C
OUTPUT DIN BIT TO LTC1283
SETB P1.3
SCLK GOES HIGH
CLR P1.3
SCLK GOES LOW
DJNZ R4, LOOP
NEXT BIT
MOV R2, A
STORE MSBs IN R2
MNEMONIC
DESCRIPTION
MOV C, P1.1
READ DATA BIT INTO CARRY
CLR A
CLEAR ACC
RLC A
ROTATE DATA BIT INTO ACC
SETB P1.3
SCLK GOES HIGH
CLR P1.3
SCLK GOES LOW
MOV C, P1.1
READ DATA BIT IN CARRY
RRC A
ROTATE RIGHT INTO ACC
RRC A
ROTATE RIGHT INTO ACC
MOV R3, A
STORE LSBs IN R3
SETB P1.3
SCLK GOES HIGH
CLR P1.3
SCLK GOES LOW
SETB P1.4
CS GOES HIGH
MOV R5, #07H
LOAD COUNTER
DELAY:
DJNZ R5, DELAY
DELAY FOR LTC1283 TO PERFORM
CONVERSION
AJMP CONTINUE
REPEAT PROGRAM
83CL410 Code
Figure 5. Several LTC1283s Sharing One 3-Wire Serial Interface
ANALOG CONSIDERATIONS
1. Grounding
The LTC1283 should be used with an analog ground plane
and single point grounding techniques.
Pin 11 (AGND) should be tied directly to this ground plane.
Pin 10 (DGND) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
Pin 20 (VCC) should be bypassed to the ground plane with
a 4.7
μF tantalum with leads as short as possible. Pin 12
(V –) should be bypassed with a 0.1
μF ceramic disk. For
single supply applications, V – can be tied to the ground
plane.
It is also recommended that pin 13 (REF –) and pin 9 (COM)
be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce errors
8 CHANNELS
3
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1283s
2
10
OUTPUT PORT
SERIAL DATA
MPU
LTC1283 F05
LTC1283
CS
LTC1283
CS
LTC1283
CS
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